| Message ID | 20210112013255.415253-1-danny@kdrag0n.dev (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | b4791e695526939be3c4f043fe69222d2ba7c171 |
| Headers | show |
| Series | [1/2] arm64: dts: qcom: sm8250: Define CPU topology | expand |
Hello: This series was applied to qcom/linux.git (refs/heads/for-next): On Mon, 11 Jan 2021 17:32:53 -0800 you wrote: > sm8250 has a big.LITTLE CPU setup with DynamIQ, so all cores are within > the same CPU cluster and LLC (Last-Level Cache) domain. Define this > topology to help the scheduler make decisions. > > Signed-off-by: Danny Lin <danny@kdrag0n.dev> > --- > arch/arm64/boot/dts/qcom/sm8250.dtsi | 36 ++++++++++++++++++++++++++++ > 1 file changed, 36 insertions(+) Here is the summary with links: - [1/2] arm64: dts: qcom: sm8250: Define CPU topology https://git.kernel.org/qcom/c/b4791e695526 - [2/2] arm64: dts: qcom: sm8250: Add CPU capacities and energy model https://git.kernel.org/qcom/c/6aabed5526ee You are awesome, thank you! -- Deet-doot-dot, I am a bot. https://korg.docs.kernel.org/patchwork/pwbot.html
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 65acd1f381eb..30ccadb753a5 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -199,6 +199,42 @@ L2_700: l2-cache { next-level-cache = <&L3_0>; }; }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + + core4 { + cpu = <&CPU4>; + }; + + core5 { + cpu = <&CPU5>; + }; + + core6 { + cpu = <&CPU6>; + }; + + core7 { + cpu = <&CPU7>; + }; + }; + }; }; firmware {
sm8250 has a big.LITTLE CPU setup with DynamIQ, so all cores are within the same CPU cluster and LLC (Last-Level Cache) domain. Define this topology to help the scheduler make decisions. Signed-off-by: Danny Lin <danny@kdrag0n.dev> --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 36 ++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+)