From patchwork Thu Jan 14 23:40:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 12021109 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8535EC433E9 for ; Thu, 14 Jan 2021 23:42:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5E00423A59 for ; Thu, 14 Jan 2021 23:42:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731070AbhANXmM (ORCPT ); Thu, 14 Jan 2021 18:42:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43096 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731037AbhANXmL (ORCPT ); Thu, 14 Jan 2021 18:42:11 -0500 Received: from mail-pj1-x1036.google.com (mail-pj1-x1036.google.com [IPv6:2607:f8b0:4864:20::1036]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 26128C061793 for ; Thu, 14 Jan 2021 15:40:54 -0800 (PST) Received: by mail-pj1-x1036.google.com with SMTP id md11so4020768pjb.0 for ; Thu, 14 Jan 2021 15:40:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Q86Uq39kF8Izless20lhwV7RldITJfPHzjplumZKKI8=; b=HvV8loM/5Wc3tTQUEaDMeVNQC6pGH3KzlsUhPabq6hf2LsCeAwPn80SUEGwvIh7n7Z 9r2ERtZBQSw+gafo60uWTEeYxkPI3PWj4S137Xu6H6pylfkTmFsJLtHSNC6b4J5gzCkE 9eFdF8SX56161ylOOsEQ3Ys9rwCRfu1tBEtOU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Q86Uq39kF8Izless20lhwV7RldITJfPHzjplumZKKI8=; b=Rk6PmP+dT/3Yt5Re/AQkLq+vEDnj56jquxvrGYtfLzA8e27b4lZqE0SiWXFP3Clb/G 0+9QqSplAbE24ytXHYRsYRquPXknndbS5WkyatzOJVHGl2qHEVIy6tMr5koLiJbU5C06 OHUaW9Tx+pNAVqATGmvriK7guGlnZrjVZOnAFDgVHyqPCUQ03oRwgfaeGa36QNX2TeWl Kpe+n7onw7BM6nshvuDoyBI+bM4as6VRy7lTpWB0B0AI4H90dKTYgjEJMUkdDkxcXji+ hpZfZ9llpgFBv74Oc80G+cOEni3PQ++3NWYrwUXl4f6BPZKa++o4PF1LR5ieWTzLPSd1 DnYQ== X-Gm-Message-State: AOAM533yCt6ySs6fGk/30Ab5oWpSB48DZQa53AqS2jU5DlhkuNgfg0ap ThjDVP2dfhPxSN0+C27PXUi/xg== X-Google-Smtp-Source: ABdhPJyNFjW5H2OxoC30TO+bl5lQRqLQZkFSxFgLLb+XdKJIv2USPjBdhtesQzHM2eypDY5p7HSMjg== X-Received: by 2002:a17:90b:e88:: with SMTP id fv8mr7386990pjb.126.1610667653718; Thu, 14 Jan 2021 15:40:53 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:42b0:34ff:fe3d:58e6]) by smtp.gmail.com with ESMTPSA id x1sm6498804pfj.95.2021.01.14.15.40.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jan 2021 15:40:53 -0800 (PST) From: Douglas Anderson To: Marc Zyngier , Thomas Gleixner , Jason Cooper , Linus Walleij Cc: Neeraj Upadhyay , Bjorn Andersson , Rajendra Nayak , Srinivas Ramana , linux-arm-msm@vger.kernel.org, Stephen Boyd , Maulik Shah , linux-gpio@vger.kernel.org, Douglas Anderson , Andy Gross , linux-kernel@vger.kernel.org Subject: [PATCH v6 3/4] pinctrl: qcom: Properly clear "intr_ack_high" interrupts when unmasking Date: Thu, 14 Jan 2021 15:40:26 -0800 Message-Id: <20210114154004.v6.3.I32d0f4e174d45363b49ab611a13c3da8f1e87d0f@changeid> X-Mailer: git-send-email 2.30.0.284.gd98b1dd5eaa7-goog In-Reply-To: <20210114154004.v6.1.I3ad184e3423d8e479bc3e86f5b393abb1704a1d1@changeid> References: <20210114154004.v6.1.I3ad184e3423d8e479bc3e86f5b393abb1704a1d1@changeid> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In commit 4b7618fdc7e6 ("pinctrl: qcom: Add irq_enable callback for msm gpio") we tried to Ack interrupts during unmask. However, that patch forgot to check "intr_ack_high" so, presumably, it only worked for a certain subset of SoCs. Let's add a small accessor so we don't need to open-code the logic in both places. This was found by code inspection. I don't have any access to the hardware in question nor software that needs the Ack during unmask. Fixes: 4b7618fdc7e6 ("pinctrl: qcom: Add irq_enable callback for msm gpio") Signed-off-by: Douglas Anderson Reviewed-by: Maulik Shah Tested-by: Maulik Shah Reviewed-by: Stephen Boyd Reviewed-by: Bjorn Andersson --- It should be noted that this code will be moved in the next patch. In theory this could be squashed into the next patch but it seems more documenting to have this as a separate patch. Changes in v6: - Remove unneeded parenthesis. Changes in v5: - ("pinctrl: qcom: Properly clear "intr_ack_high" interrupts...") new for v5. drivers/pinctrl/qcom/pinctrl-msm.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 2f363c28d9d9..192ed31eabf4 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -96,6 +96,14 @@ MSM_ACCESSOR(intr_cfg) MSM_ACCESSOR(intr_status) MSM_ACCESSOR(intr_target) +static void msm_ack_intr_status(struct msm_pinctrl *pctrl, + const struct msm_pingroup *g) +{ + u32 val = g->intr_ack_high ? BIT(g->intr_status_bit) : 0; + + msm_writel_intr_status(val, pctrl, g); +} + static int msm_get_groups_count(struct pinctrl_dev *pctldev) { struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); @@ -797,7 +805,7 @@ static void msm_gpio_irq_clear_unmask(struct irq_data *d, bool status_clear) * when the interrupt is not in use. */ if (status_clear) - msm_writel_intr_status(0, pctrl, g); + msm_ack_intr_status(pctrl, g); val = msm_readl_intr_cfg(pctrl, g); val |= BIT(g->intr_raw_status_bit); @@ -890,7 +898,6 @@ static void msm_gpio_irq_ack(struct irq_data *d) struct msm_pinctrl *pctrl = gpiochip_get_data(gc); const struct msm_pingroup *g; unsigned long flags; - u32 val; if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) { if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) @@ -902,8 +909,7 @@ static void msm_gpio_irq_ack(struct irq_data *d) raw_spin_lock_irqsave(&pctrl->lock, flags); - val = g->intr_ack_high ? BIT(g->intr_status_bit) : 0; - msm_writel_intr_status(val, pctrl, g); + msm_ack_intr_status(pctrl, g); if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) msm_gpio_update_dual_edge_pos(pctrl, g, d);