From patchwork Sun Jan 17 01:31:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12025165 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3AF58C433DB for ; Sun, 17 Jan 2021 01:32:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EC14D22C7D for ; Sun, 17 Jan 2021 01:32:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727737AbhAQBcP (ORCPT ); Sat, 16 Jan 2021 20:32:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32814 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727520AbhAQBcM (ORCPT ); Sat, 16 Jan 2021 20:32:12 -0500 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4505BC0613D6 for ; Sat, 16 Jan 2021 17:31:21 -0800 (PST) Received: by mail-lf1-x130.google.com with SMTP id 23so18898394lfg.10 for ; Sat, 16 Jan 2021 17:31:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TqPs2Rrxfynaryc0Bxb5YregqUil4E5/ABS7A7T0BQ8=; b=KGBEtXkESMkft2WFrHsXWAyTDavpVgH1cEfLREQnwb1BeC/ljj6rk7I4j7hvCgLQOy Mvn8KPnxvo/ZY7YX/8Jw46/d83rPeglNMiKLym3TDjlHUkq9ydGmbqt3Kbnf4lf5245I DYJse/VrQ8pTec0C1amc18zrMLL/FLmBx4NSbxQ4uzsyRT90pBE/6uoP2kbMN8JlwyN1 IuLT4M6hsWKru9Orb1ssdX978WYS9AweeZDzovCSgc3ghUeROGVFdRNhavBviXcFEBgf tmkMw/Smxm8zbmClrWM2tVIBI/3SJyv9kRFF+EZjK3NklGyaA2V6mhw0NMuhS28F+TUO bpQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TqPs2Rrxfynaryc0Bxb5YregqUil4E5/ABS7A7T0BQ8=; b=s4K6pUTvi2WKZjvTwX+RWojPOFySsRuiYuV15RJ2eFweHnIFJBCYipbnmUJ3EEhnW0 //RRXpqot2HFkXGlyTWRh138i/NuB1oCtWg62ahEmR2nBrcSpajXNmeoHKWOIhLfGZPR 3ElMUreimQTHy6pKeR1YKRJIHuySfM2/xc5g3vUFaMZ9TYH4ozrI3NglFUsRwuaD2Sv2 pKr6F1Q0PEAGR0YZuPn5/lpODV4KOzOo532JgqV3RNKvU9jT9etw4X79EVqh5Z+UbWnI 4pizDbh+lwjlzvJlw/Kv2E+/TOwqHPD0/T0RbE9KGZnrZ/+W9FWtOpNqDfa4XNokQx83 FSpw== X-Gm-Message-State: AOAM532L6WOCK234JQTKhvXKWU+gR2dr58xnOPIHR1VG8qfEsD0INUmp pv8Vb34s5iWgrEav8cjsqxLoECB5/DOLgUYd X-Google-Smtp-Source: ABdhPJxBy/AxQ1DlYezLG9RQrHb26ETt2mxrHycxSKXf3pnEPS9WJcXast9Tu1QlFdtJgtq7Gt0drA== X-Received: by 2002:a19:c215:: with SMTP id l21mr8134361lfc.142.1610847079827; Sat, 16 Jan 2021 17:31:19 -0800 (PST) Received: from eriador.lumag.spb.ru ([94.25.228.101]) by smtp.gmail.com with ESMTPSA id c1sm1286298ljd.117.2021.01.16.17.31.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Jan 2021 17:31:19 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Lorenzo Pieralisi Cc: linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam , linux-pci@vger.kernel.org Subject: [PATCH v5 2/2] PCI: qcom: add support for ddrss_sf_tbu clock Date: Sun, 17 Jan 2021 04:31:14 +0300 Message-Id: <20210117013114.441973-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210117013114.441973-1-dmitry.baryshkov@linaro.org> References: <20210117013114.441973-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On SM8250 additional clock is required for PCIe devices to access NOC. Update PCIe controller driver to control this clock. Signed-off-by: Dmitry Baryshkov Fixes: e1dd639e374a ("PCI: qcom: Add SM8250 SoC support") Reviewed-by: Manivannan Sadhasivam Acked-by: Stanimir Varbanov --- drivers/pci/controller/dwc/pcie-qcom.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index affa2713bf80..ab21aa01c95d 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -159,8 +159,10 @@ struct qcom_pcie_resources_2_3_3 { struct reset_control *rst[7]; }; +/* 6 clocks typically, 7 for sm8250 */ struct qcom_pcie_resources_2_7_0 { - struct clk_bulk_data clks[6]; + struct clk_bulk_data clks[7]; + int num_clks; struct regulator_bulk_data supplies[2]; struct reset_control *pci_reset; struct clk *pipe_clk; @@ -1152,8 +1154,14 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) res->clks[3].id = "bus_slave"; res->clks[4].id = "slave_q2a"; res->clks[5].id = "tbu"; + if (of_device_is_compatible(dev->of_node, "qcom,pcie-sm8250")) { + res->clks[6].id = "ddrss_sf_tbu"; + res->num_clks = 7; + } else { + res->num_clks = 6; + } - ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); + ret = devm_clk_bulk_get(dev, res->num_clks, res->clks); if (ret < 0) return ret; @@ -1175,7 +1183,7 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) return ret; } - ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); + ret = clk_bulk_prepare_enable(res->num_clks, res->clks); if (ret < 0) goto err_disable_regulators; @@ -1227,7 +1235,7 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) return 0; err_disable_clocks: - clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); + clk_bulk_disable_unprepare(res->num_clks, res->clks); err_disable_regulators: regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); @@ -1238,7 +1246,7 @@ static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; - clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); + clk_bulk_disable_unprepare(res->num_clks, res->clks); regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); }