| Message ID | 20210124135409.5473-3-jonathan.albrieux@gmail.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add initial support for BQ Aquaris X5 | expand |
On 24.01.2021 14:54, Jonathan Albrieux wrote: > MSM8916 has another I2C QUP controller that can be enabled on > GPIO 10 and 11. > > Add blsp_i2c3 to msm8916.dtsi and disable it by default. > > Signed-off-by: Jonathan Albrieux <jonathan.albrieux@gmail.com> > --- > arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 16 ++++++++++++++++ > arch/arm64/boot/dts/qcom/msm8916.dtsi | 15 +++++++++++++++ > 2 files changed, 31 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi > index 4dc437f13fa5..7dedb91b9930 100644 > --- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi > @@ -220,6 +220,22 @@ > bias-disable; > }; > > + i2c3_default: i2c3-default { > + pins = "gpio10", "gpio11"; > + function = "blsp_i2c3"; > + > + drive-strength = <2>; > + bias-disable; > + }; > + > + i2c3_sleep: i2c3-sleep { > + pins = "gpio10", "gpio11"; > + function = "gpio"; > + > + drive-strength = <2>; > + bias-disable; > + }; > + > i2c4_default: i2c4-default { > pins = "gpio14", "gpio15"; > function = "blsp_i2c4"; > diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi > index 402e891a84ab..1045d7e518f3 100644 > --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi > @@ -1528,6 +1528,21 @@ > status = "disabled"; > }; > > + blsp_i2c3: i2c@78b7000 { > + compatible = "qcom,i2c-qup-v2.2.1"; > + reg = <0x078b7000 0x500>; > + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&gcc GCC_BLSP1_AHB_CLK>, > + <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; > + clock-names = "iface", "core"; > + pinctrl-names = "default", "sleep"; > + pinctrl-0 = <&i2c3_default>; > + pinctrl-1 = <&i2c3_sleep>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > blsp_spi3: spi@78b7000 { > compatible = "qcom,spi-qup-v2.2.1"; > reg = <0x078b7000 0x500>; > Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Things to consider for the future: * DMA on I2C * Merging in the -pins.dtsi to 8916.dtsi? Konrad
On Sun, Jan 24, 2021 at 02:54:06PM +0100, Jonathan Albrieux wrote: > MSM8916 has another I2C QUP controller that can be enabled on > GPIO 10 and 11. > > Add blsp_i2c3 to msm8916.dtsi and disable it by default. > > Signed-off-by: Jonathan Albrieux <jonathan.albrieux@gmail.com> Reviewed-by: Stephan Gerhold <stephan@gerhold.net> > --- > arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 16 ++++++++++++++++ > arch/arm64/boot/dts/qcom/msm8916.dtsi | 15 +++++++++++++++ > 2 files changed, 31 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi > index 4dc437f13fa5..7dedb91b9930 100644 > --- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi > @@ -220,6 +220,22 @@ > bias-disable; > }; > > + i2c3_default: i2c3-default { > + pins = "gpio10", "gpio11"; > + function = "blsp_i2c3"; > + > + drive-strength = <2>; > + bias-disable; > + }; > + > + i2c3_sleep: i2c3-sleep { > + pins = "gpio10", "gpio11"; > + function = "gpio"; > + > + drive-strength = <2>; > + bias-disable; > + }; > + > i2c4_default: i2c4-default { > pins = "gpio14", "gpio15"; > function = "blsp_i2c4"; > diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi > index 402e891a84ab..1045d7e518f3 100644 > --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi > @@ -1528,6 +1528,21 @@ > status = "disabled"; > }; > > + blsp_i2c3: i2c@78b7000 { > + compatible = "qcom,i2c-qup-v2.2.1"; > + reg = <0x078b7000 0x500>; > + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&gcc GCC_BLSP1_AHB_CLK>, > + <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; > + clock-names = "iface", "core"; > + pinctrl-names = "default", "sleep"; > + pinctrl-0 = <&i2c3_default>; > + pinctrl-1 = <&i2c3_sleep>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > blsp_spi3: spi@78b7000 { > compatible = "qcom,spi-qup-v2.2.1"; > reg = <0x078b7000 0x500>; > -- > 2.17.1 >
diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi index 4dc437f13fa5..7dedb91b9930 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi @@ -220,6 +220,22 @@ bias-disable; }; + i2c3_default: i2c3-default { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + + drive-strength = <2>; + bias-disable; + }; + + i2c3_sleep: i2c3-sleep { + pins = "gpio10", "gpio11"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + i2c4_default: i2c4-default { pins = "gpio14", "gpio15"; function = "blsp_i2c4"; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 402e891a84ab..1045d7e518f3 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1528,6 +1528,21 @@ status = "disabled"; }; + blsp_i2c3: i2c@78b7000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b7000 0x500>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c3_default>; + pinctrl-1 = <&i2c3_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + blsp_spi3: spi@78b7000 { compatible = "qcom,spi-qup-v2.2.1"; reg = <0x078b7000 0x500>;
MSM8916 has another I2C QUP controller that can be enabled on GPIO 10 and 11. Add blsp_i2c3 to msm8916.dtsi and disable it by default. Signed-off-by: Jonathan Albrieux <jonathan.albrieux@gmail.com> --- arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 16 ++++++++++++++++ arch/arm64/boot/dts/qcom/msm8916.dtsi | 15 +++++++++++++++ 2 files changed, 31 insertions(+)