diff mbox series

[3/4] phy: qcom-qmp: Add UFS v4 registers found in SM8350

Message ID 20210125100906.4004908-4-vkoul@kernel.org (mailing list archive)
State New
Headers show
Series Add Support for SM8350 UFS | expand

Commit Message

Vinod Koul Jan. 25, 2021, 10:09 a.m. UTC
Add the registers for few new registers found in SM8350. Also the UFS
phy used in SM8350 seems to have different offsets than V4 phy, although
it claims it is v4 phy, so add the new offsets with SM8350 tag instead
of V4 tag.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
 drivers/phy/qualcomm/phy-qcom-qmp.h | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

Comments

Bjorn Andersson Jan. 25, 2021, 5:11 p.m. UTC | #1
On Mon 25 Jan 04:09 CST 2021, Vinod Koul wrote:

> Add the registers for few new registers found in SM8350. Also the UFS
> phy used in SM8350 seems to have different offsets than V4 phy, although
> it claims it is v4 phy, so add the new offsets with SM8350 tag instead
> of V4 tag.
> 

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>

> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
>  drivers/phy/qualcomm/phy-qcom-qmp.h | 27 +++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
> index dff7be5a1cc1..bba1d5e3eb73 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
> @@ -451,6 +451,7 @@
>  #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 		0x40
>  #define QSERDES_V4_TX_LANE_MODE_1			0x84
>  #define QSERDES_V4_TX_LANE_MODE_2			0x88
> +#define QSERDES_V4_TX_LANE_MODE_3			0x8C
>  #define QSERDES_V4_TX_RCV_DETECT_LVL_2			0x9c
>  #define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1	0xd8
>  #define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1	0xdC
> @@ -459,6 +460,13 @@
>  #define QSERDES_V4_TX_TRAN_DRVR_EMP_EN			0xb8
>  #define QSERDES_V4_TX_PI_QEC_CTRL		0x104
>  
> +/* Only for SM8350 QMP V4 Phy TX offsets different from V4 */
> +#define QSERDES_SM8350_TX_PWM_GEAR_1_DIVIDER_BAND0_1	0x178
> +#define QSERDES_SM8350_TX_PWM_GEAR_2_DIVIDER_BAND0_1	0x17c
> +#define QSERDES_SM8350_TX_PWM_GEAR_3_DIVIDER_BAND0_1	0x180
> +#define QSERDES_SM8350_TX_PWM_GEAR_4_DIVIDER_BAND0_1	0x184
> +#define QSERDES_SM8350_TX_TRAN_DRVR_EMP_EN		0xc0
> +
>  /* Only for QMP V4 PHY - RX registers */
>  #define QSERDES_V4_RX_UCDR_FO_GAIN			0x008
>  #define QSERDES_V4_RX_UCDR_SO_GAIN			0x014
> @@ -514,6 +522,24 @@
>  #define QSERDES_V4_RX_DCC_CTRL1				0x1bc
>  #define QSERDES_V4_RX_VTH_CODE				0x1c4
>  
> +/* Only for SM8350 QMP V4 Phy RX offsets different from V4 */
> +#define QSERDES_SM8350_RX_RX_MODE_00_LOW		0x15c
> +#define QSERDES_SM8350_RX_RX_MODE_00_HIGH		0x160
> +#define QSERDES_SM8350_RX_RX_MODE_00_HIGH2		0x164
> +#define QSERDES_SM8350_RX_RX_MODE_00_HIGH3		0x168
> +#define QSERDES_SM8350_RX_RX_MODE_00_HIGH4		0x16c
> +#define QSERDES_SM8350_RX_RX_MODE_01_LOW		0x170
> +#define QSERDES_SM8350_RX_RX_MODE_01_HIGH		0x174
> +#define QSERDES_SM8350_RX_RX_MODE_01_HIGH2		0x178
> +#define QSERDES_SM8350_RX_RX_MODE_01_HIGH3		0x17c
> +#define QSERDES_SM8350_RX_RX_MODE_01_HIGH4		0x180
> +#define QSERDES_SM8350_RX_RX_MODE_10_LOW		0x184
> +#define QSERDES_SM8350_RX_RX_MODE_10_HIGH		0x188
> +#define QSERDES_SM8350_RX_RX_MODE_10_HIGH2		0x18c
> +#define QSERDES_SM8350_RX_RX_MODE_10_HIGH3		0x190
> +#define QSERDES_SM8350_RX_RX_MODE_10_HIGH4		0x194
> +#define QSERDES_SM8350_RX_DCC_CTRL1			0x1a8
> +
>  /* Only for QMP V4 PHY - UFS PCS registers */
>  #define QPHY_V4_PCS_UFS_PHY_START				0x000
>  #define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL			0x004
> @@ -529,6 +555,7 @@
>  #define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL			0x124
>  #define QPHY_V4_PCS_UFS_LINECFG_DISABLE				0x148
>  #define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME			0x150
> +#define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL1				0x154
>  #define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2				0x158
>  #define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND			0x160
>  #define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND				0x168
> -- 
> 2.26.2
>
Jack Pham Jan. 25, 2021, 5:36 p.m. UTC | #2
Hi Vinod,

On Mon, Jan 25, 2021 at 03:39:05PM +0530, Vinod Koul wrote:
> Add the registers for few new registers found in SM8350. Also the UFS
> phy used in SM8350 seems to have different offsets than V4 phy, although
> it claims it is v4 phy, so add the new offsets with SM8350 tag instead
> of V4 tag.

Actually I believe SM8350 UFS PHY is on V5, as the internal IP revision
shows 5.0.0. So IMO some of the below definitions should just be using
the V5 macros for consistency with the ones I recently added for USB3.

And like USB3 QMP, it seems we have mixed usage of V4/V5 macros in the
sequence tables, mainly wherever the offsets are identical between IP
revisions. Hope this doesn't turn out to be a maintenance nightmare...

> ---
>  drivers/phy/qualcomm/phy-qcom-qmp.h | 27 +++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
> index dff7be5a1cc1..bba1d5e3eb73 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
> @@ -451,6 +451,7 @@
>  #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 		0x40
>  #define QSERDES_V4_TX_LANE_MODE_1			0x84
>  #define QSERDES_V4_TX_LANE_MODE_2			0x88
> +#define QSERDES_V4_TX_LANE_MODE_3			0x8C
>  #define QSERDES_V4_TX_RCV_DETECT_LVL_2			0x9c
>  #define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1	0xd8
>  #define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1	0xdC
> @@ -459,6 +460,13 @@
>  #define QSERDES_V4_TX_TRAN_DRVR_EMP_EN			0xb8
>  #define QSERDES_V4_TX_PI_QEC_CTRL		0x104
>  
> +/* Only for SM8350 QMP V4 Phy TX offsets different from V4 */
> +#define QSERDES_SM8350_TX_PWM_GEAR_1_DIVIDER_BAND0_1	0x178
> +#define QSERDES_SM8350_TX_PWM_GEAR_2_DIVIDER_BAND0_1	0x17c
> +#define QSERDES_SM8350_TX_PWM_GEAR_3_DIVIDER_BAND0_1	0x180
> +#define QSERDES_SM8350_TX_PWM_GEAR_4_DIVIDER_BAND0_1	0x184
> +#define QSERDES_SM8350_TX_TRAN_DRVR_EMP_EN		0xc0

These could be augmented to the V5 TX defintions? Although they are not
present for USB, so not sure if you want to add "V5_UFS" to the prefix.
But since they are at offsets past the end of the USB TX bank it should
also be ok to share in the QSERDES_V5_TX namespace.

> +
>  /* Only for QMP V4 PHY - RX registers */
>  #define QSERDES_V4_RX_UCDR_FO_GAIN			0x008
>  #define QSERDES_V4_RX_UCDR_SO_GAIN			0x014
> @@ -514,6 +522,24 @@
>  #define QSERDES_V4_RX_DCC_CTRL1				0x1bc
>  #define QSERDES_V4_RX_VTH_CODE				0x1c4
>  
> +/* Only for SM8350 QMP V4 Phy RX offsets different from V4 */
> +#define QSERDES_SM8350_RX_RX_MODE_00_LOW		0x15c
> +#define QSERDES_SM8350_RX_RX_MODE_00_HIGH		0x160
> +#define QSERDES_SM8350_RX_RX_MODE_00_HIGH2		0x164
> +#define QSERDES_SM8350_RX_RX_MODE_00_HIGH3		0x168
> +#define QSERDES_SM8350_RX_RX_MODE_00_HIGH4		0x16c
> +#define QSERDES_SM8350_RX_RX_MODE_01_LOW		0x170
> +#define QSERDES_SM8350_RX_RX_MODE_01_HIGH		0x174
> +#define QSERDES_SM8350_RX_RX_MODE_01_HIGH2		0x178
> +#define QSERDES_SM8350_RX_RX_MODE_01_HIGH3		0x17c
> +#define QSERDES_SM8350_RX_RX_MODE_01_HIGH4		0x180
> +#define QSERDES_SM8350_RX_RX_MODE_10_LOW		0x184
> +#define QSERDES_SM8350_RX_RX_MODE_10_HIGH		0x188
> +#define QSERDES_SM8350_RX_RX_MODE_10_HIGH2		0x18c
> +#define QSERDES_SM8350_RX_RX_MODE_10_HIGH3		0x190
> +#define QSERDES_SM8350_RX_RX_MODE_10_HIGH4		0x194
> +#define QSERDES_SM8350_RX_DCC_CTRL1			0x1a8

These are identical to the "V5" offsets I had added for SM8350 USB.

Thanks,
Jack
diff mbox series

Patch

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index dff7be5a1cc1..bba1d5e3eb73 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -451,6 +451,7 @@ 
 #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 		0x40
 #define QSERDES_V4_TX_LANE_MODE_1			0x84
 #define QSERDES_V4_TX_LANE_MODE_2			0x88
+#define QSERDES_V4_TX_LANE_MODE_3			0x8C
 #define QSERDES_V4_TX_RCV_DETECT_LVL_2			0x9c
 #define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1	0xd8
 #define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1	0xdC
@@ -459,6 +460,13 @@ 
 #define QSERDES_V4_TX_TRAN_DRVR_EMP_EN			0xb8
 #define QSERDES_V4_TX_PI_QEC_CTRL		0x104
 
+/* Only for SM8350 QMP V4 Phy TX offsets different from V4 */
+#define QSERDES_SM8350_TX_PWM_GEAR_1_DIVIDER_BAND0_1	0x178
+#define QSERDES_SM8350_TX_PWM_GEAR_2_DIVIDER_BAND0_1	0x17c
+#define QSERDES_SM8350_TX_PWM_GEAR_3_DIVIDER_BAND0_1	0x180
+#define QSERDES_SM8350_TX_PWM_GEAR_4_DIVIDER_BAND0_1	0x184
+#define QSERDES_SM8350_TX_TRAN_DRVR_EMP_EN		0xc0
+
 /* Only for QMP V4 PHY - RX registers */
 #define QSERDES_V4_RX_UCDR_FO_GAIN			0x008
 #define QSERDES_V4_RX_UCDR_SO_GAIN			0x014
@@ -514,6 +522,24 @@ 
 #define QSERDES_V4_RX_DCC_CTRL1				0x1bc
 #define QSERDES_V4_RX_VTH_CODE				0x1c4
 
+/* Only for SM8350 QMP V4 Phy RX offsets different from V4 */
+#define QSERDES_SM8350_RX_RX_MODE_00_LOW		0x15c
+#define QSERDES_SM8350_RX_RX_MODE_00_HIGH		0x160
+#define QSERDES_SM8350_RX_RX_MODE_00_HIGH2		0x164
+#define QSERDES_SM8350_RX_RX_MODE_00_HIGH3		0x168
+#define QSERDES_SM8350_RX_RX_MODE_00_HIGH4		0x16c
+#define QSERDES_SM8350_RX_RX_MODE_01_LOW		0x170
+#define QSERDES_SM8350_RX_RX_MODE_01_HIGH		0x174
+#define QSERDES_SM8350_RX_RX_MODE_01_HIGH2		0x178
+#define QSERDES_SM8350_RX_RX_MODE_01_HIGH3		0x17c
+#define QSERDES_SM8350_RX_RX_MODE_01_HIGH4		0x180
+#define QSERDES_SM8350_RX_RX_MODE_10_LOW		0x184
+#define QSERDES_SM8350_RX_RX_MODE_10_HIGH		0x188
+#define QSERDES_SM8350_RX_RX_MODE_10_HIGH2		0x18c
+#define QSERDES_SM8350_RX_RX_MODE_10_HIGH3		0x190
+#define QSERDES_SM8350_RX_RX_MODE_10_HIGH4		0x194
+#define QSERDES_SM8350_RX_DCC_CTRL1			0x1a8
+
 /* Only for QMP V4 PHY - UFS PCS registers */
 #define QPHY_V4_PCS_UFS_PHY_START				0x000
 #define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL			0x004
@@ -529,6 +555,7 @@ 
 #define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL			0x124
 #define QPHY_V4_PCS_UFS_LINECFG_DISABLE				0x148
 #define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME			0x150
+#define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL1				0x154
 #define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2				0x158
 #define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND			0x160
 #define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND				0x168