| Message ID | 20210128175225.3102958-5-dmitry.baryshkov@linaro.org (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | Add support for Qualcomm QCA639x chips family | expand |
On 28/01/2021 22:21, Rob Herring wrote: > On Thu, Jan 28, 2021 at 11:52 AM Dmitry Baryshkov > <dmitry.baryshkov@linaro.org> wrote: >> >> If QCA6391 chip (connected to PCIe0) is not powered at the PCIe probe >> time, PCIe0 bus probe will timeout and the device will not be detected. >> So use qca6391 as pcie0's bridge power-domain. This allows us to make >> sure that QCA6391 chip is powered on before PCIe0 probe happens. >> >> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >> --- >> arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 12 ++++++++++++ >> 1 file changed, 12 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts >> index 2b0c1cc9333b..b39a9729395f 100644 >> --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts >> +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts >> @@ -581,6 +581,18 @@ &pcie0 { >> wake-gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>; >> pinctrl-names = "default"; >> pinctrl-0 = <&pcie0_default_state>; >> + >> + bridge@0,0 { >> + compatible = "pci17cb,010b"; >> + reg = <0 0 0 0 0>; >> + >> + #address-cells = <3>; >> + #size-cells = <2>; >> + #interrupt-cells = <1>; >> + >> + /* Power on QCA639x chip sitting behind this bridge. */ >> + power-domains = <&qca6391>; > > This all must be in a child node of the bridge representing the wifi > device. Ack > And all the regulators in the &qca6391 node should just be in > the child node here. The indirection is pointless from a DT > perspective. It is not an indirection. The qca6391 node is shared between WiFi sitting on PCIe and BT sitting on serial port. One can not say that BT is powered by WiFi or vice versa. Thus there is a need for separate 'power domain' node.
diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 2b0c1cc9333b..b39a9729395f 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -581,6 +581,18 @@ &pcie0 { wake-gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; + + bridge@0,0 { + compatible = "pci17cb,010b"; + reg = <0 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + /* Power on QCA639x chip sitting behind this bridge. */ + power-domains = <&qca6391>; + }; }; &pcie0_phy {
If QCA6391 chip (connected to PCIe0) is not powered at the PCIe probe time, PCIe0 bus probe will timeout and the device will not be detected. So use qca6391 as pcie0's bridge power-domain. This allows us to make sure that QCA6391 chip is powered on before PCIe0 probe happens. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+)