| Message ID | 20210209202849.1148569-5-dmitry.baryshkov@linaro.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | arm64: dts: qcom: qrb5165-rb5: use GPIO as SPI0 CS | expand |
Hi, On Tue, Feb 9, 2021 at 12:29 PM Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote: > > GENI SPI controller shows several issues if it manages the CS on its own > (see 37dd4b777942 ("arm64: dts: qcom: sc7180: Provide pinconf for SPI to > use GPIO for CS")) for the details. Configure SPI0 CS pin as a GPIO. Slight nit that it might be nice to mention that (presumably) the only reason this actually fixed any bugs for you is because you have extra non-mainline patches to the SPI driver that (presumably) break non-GPIO chip select. If it's the same non-mainline patch that I reviewed to add GPI/GSI support to the SPI driver then I'm not terribly surprised. I believe when I reviewed it I found that it was breaking the non-GPI/GSI code paths. See <https://lore.kernel.org/r/CAD=FV=XmfpQXhK_tKor-ta+5dqT-aq7OnV1e=VY-vMuXmUQEfQ@mail.gmail.com> where I said "Why are you changing this? [...] I'd imagine this change breaks stuff?" Really the only benefit from this change _should_ be better performance. > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) Other than the nit about the CL desc: Reviewed-by: Douglas Anderson <dianders@chromium.org>
diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 922f329d623a..d329829c61fa 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -815,7 +815,7 @@ &pm8150_rtc { status = "okay"; }; -&qup_spi0_cs { +&qup_spi0_cs_gpio { drive-strength = <6>; bias-disable; }; @@ -963,7 +963,8 @@ codec { &spi0 { status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; + pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs_gpio>; + cs-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>; can@0 { compatible = "microchip,mcp2518fd";
GENI SPI controller shows several issues if it manages the CS on its own (see 37dd4b777942 ("arm64: dts: qcom: sc7180: Provide pinconf for SPI to use GPIO for CS")) for the details. Configure SPI0 CS pin as a GPIO. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)