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[v4,4/4] arm64: dts: qcom: qrb5165-rb5: switch into using GPIO for SPI0 CS

Message ID 20210210133458.1201066-5-dmitry.baryshkov@linaro.org (mailing list archive)
State Accepted
Commit e9269650db2f5b4aeeafced1a42b2e51d10bcdf5
Headers show
Series arm64: dts: qcom: qrb5165-rb5: use GPIO as SPI0 CS | expand

Commit Message

Dmitry Baryshkov Feb. 10, 2021, 1:34 p.m. UTC 
On the GENI SPI controller is is not very efficient if the chip select
line is controlled by the QUP itself (see 37dd4b777942 ("arm64: dts:
qcom: sc7180: Provide pinconf for SPI to use GPIO for CS") for the
details). Configure SPI0 CS pin as a GPIO.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
---
 arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
index 638231f48388..f18c703d024a 100644
--- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
+++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
@@ -953,7 +953,8 @@  codec {
 &spi0 {
 	status = "okay";
 	pinctrl-names = "default";
-	pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
+	pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs_gpio>;
+	cs-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
 
 	can@0 {
 		compatible = "microchip,mcp2518fd";
@@ -1356,7 +1357,7 @@  &vamacro {
 };
 
 /* PINCTRL - additions to nodes defined in sm8250.dtsi */
-&qup_spi0_cs {
+&qup_spi0_cs_gpio {
 	drive-strength = <6>;
 	bias-disable;
 };