diff mbox series

[v5,20/22] arm64: dts: sdm845: Add CAMSS ISP node

Message ID 20210217112122.424236-21-robert.foss@linaro.org (mailing list archive)
State New
Headers show
Series Add support for the SDM845 Camera Subsystem | expand

Commit Message

Robert Foss Feb. 17, 2021, 11:21 a.m. UTC
Add the camss dt node for sdm845.

Signed-off-by: Robert Foss <robert.foss@linaro.org>
---
 arch/arm64/boot/dts/qcom/sdm845.dtsi | 135 +++++++++++++++++++++++++++
 1 file changed, 135 insertions(+)

Comments

Andrey Konovalov Feb. 21, 2021, 6:39 p.m. UTC | #1
Hi Robert,

Thank you for your patch!

Reviewed-by: Andrey Konovalov <andrey.konovalov@linaro.org>

Thanks,
Andrey

On 17.02.2021 14:21, Robert Foss wrote:
> Add the camss dt node for sdm845.
> 
> Signed-off-by: Robert Foss <robert.foss@linaro.org>
> ---
>   arch/arm64/boot/dts/qcom/sdm845.dtsi | 135 +++++++++++++++++++++++++++
>   1 file changed, 135 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index bcf888381f14..4fe93c69908a 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -3911,6 +3911,141 @@ videocc: clock-controller@ab00000 {
>   			#reset-cells = <1>;
>   		};
>   
> +		camss: camss@a00000 {
> +			compatible = "qcom,sdm845-camss";
> +
> +			reg = <0 0xacb3000 0 0x1000>,
> +				<0 0xacba000 0 0x1000>,
> +				<0 0xacc8000 0 0x1000>,
> +				<0 0xac65000 0 0x1000>,
> +				<0 0xac66000 0 0x1000>,
> +				<0 0xac67000 0 0x1000>,
> +				<0 0xac68000 0 0x1000>,
> +				<0 0xacaf000 0 0x4000>,
> +				<0 0xacb6000 0 0x4000>,
> +				<0 0xacc4000 0 0x4000>;
> +			reg-names = "csid0",
> +				"csid1",
> +				"csid2",
> +				"csiphy0",
> +				"csiphy1",
> +				"csiphy2",
> +				"csiphy3",
> +				"vfe0",
> +				"vfe1",
> +				"vfe_lite";
> +
> +			interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
> +				<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
> +				<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
> +				<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
> +				<GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
> +				<GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
> +				<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
> +				<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
> +				<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
> +				<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "csid0",
> +				"csid1",
> +				"csid2",
> +				"csiphy0",
> +				"csiphy1",
> +				"csiphy2",
> +				"csiphy3",
> +				"vfe0",
> +				"vfe1",
> +				"vfe_lite";
> +
> +			power-domains = <&clock_camcc IFE_0_GDSC>,
> +				<&clock_camcc IFE_1_GDSC>,
> +				<&clock_camcc TITAN_TOP_GDSC>;
> +
> +			clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
> +				<&clock_camcc CAM_CC_CPAS_AHB_CLK>,
> +				<&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
> +				<&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
> +				<&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
> +				<&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
> +				<&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
> +				<&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
> +				<&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
> +				<&clock_camcc CAM_CC_CSIPHY0_CLK>,
> +				<&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,
> +				<&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
> +				<&clock_camcc CAM_CC_CSIPHY1_CLK>,
> +				<&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,
> +				<&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
> +				<&clock_camcc CAM_CC_CSIPHY2_CLK>,
> +				<&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,
> +				<&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
> +				<&clock_camcc CAM_CC_CSIPHY3_CLK>,
> +				<&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>,
> +				<&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
> +				<&gcc GCC_CAMERA_AHB_CLK>,
> +				<&gcc GCC_CAMERA_AXI_CLK>,
> +				<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
> +				<&clock_camcc CAM_CC_SOC_AHB_CLK>,
> +				<&clock_camcc CAM_CC_IFE_0_AXI_CLK>,
> +				<&clock_camcc CAM_CC_IFE_0_CLK>,
> +				<&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
> +				<&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
> +				<&clock_camcc CAM_CC_IFE_1_AXI_CLK>,
> +				<&clock_camcc CAM_CC_IFE_1_CLK>,
> +				<&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
> +				<&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
> +				<&clock_camcc CAM_CC_IFE_LITE_CLK>,
> +				<&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
> +				<&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>;
> +			clock-names = "camnoc_axi",
> +				"cpas_ahb",
> +				"cphy_rx_src",
> +				"csi0",
> +				"csi0_src",
> +				"csi1",
> +				"csi1_src",
> +				"csi2",
> +				"csi2_src",
> +				"csiphy0",
> +				"csiphy0_timer",
> +				"csiphy0_timer_src",
> +				"csiphy1",
> +				"csiphy1_timer",
> +				"csiphy1_timer_src",
> +				"csiphy2",
> +				"csiphy2_timer",
> +				"csiphy2_timer_src",
> +				"csiphy3",
> +				"csiphy3_timer",
> +				"csiphy3_timer_src",
> +				"gcc_camera_ahb",
> +				"gcc_camera_axi",
> +				"slow_ahb_src",
> +				"soc_ahb",
> +				"vfe0_axi",
> +				"vfe0",
> +				"vfe0_cphy_rx",
> +				"vfe0_src",
> +				"vfe1_axi",
> +				"vfe1",
> +				"vfe1_cphy_rx",
> +				"vfe1_src",
> +				"vfe_lite",
> +				"vfe_lite_cphy_rx",
> +				"vfe_lite_src";
> +
> +			iommus = <&apps_smmu 0x0808 0x0>,
> +				 <&apps_smmu 0x0810 0x8>,
> +				 <&apps_smmu 0x0c08 0x0>,
> +				 <&apps_smmu 0x0c10 0x8>;
> +
> +			status = "disabled";
> +
> +			ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +			};
> +		};
> +
>   		cci: cci@ac4a000 {
>   			compatible = "qcom,sdm845-cci";
>   			#address-cells = <1>;
>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index bcf888381f14..4fe93c69908a 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -3911,6 +3911,141 @@  videocc: clock-controller@ab00000 {
 			#reset-cells = <1>;
 		};
 
+		camss: camss@a00000 {
+			compatible = "qcom,sdm845-camss";
+
+			reg = <0 0xacb3000 0 0x1000>,
+				<0 0xacba000 0 0x1000>,
+				<0 0xacc8000 0 0x1000>,
+				<0 0xac65000 0 0x1000>,
+				<0 0xac66000 0 0x1000>,
+				<0 0xac67000 0 0x1000>,
+				<0 0xac68000 0 0x1000>,
+				<0 0xacaf000 0 0x4000>,
+				<0 0xacb6000 0 0x4000>,
+				<0 0xacc4000 0 0x4000>;
+			reg-names = "csid0",
+				"csid1",
+				"csid2",
+				"csiphy0",
+				"csiphy1",
+				"csiphy2",
+				"csiphy3",
+				"vfe0",
+				"vfe1",
+				"vfe_lite";
+
+			interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "csid0",
+				"csid1",
+				"csid2",
+				"csiphy0",
+				"csiphy1",
+				"csiphy2",
+				"csiphy3",
+				"vfe0",
+				"vfe1",
+				"vfe_lite";
+
+			power-domains = <&clock_camcc IFE_0_GDSC>,
+				<&clock_camcc IFE_1_GDSC>,
+				<&clock_camcc TITAN_TOP_GDSC>;
+
+			clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
+				<&clock_camcc CAM_CC_CPAS_AHB_CLK>,
+				<&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
+				<&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
+				<&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
+				<&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
+				<&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
+				<&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
+				<&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
+				<&clock_camcc CAM_CC_CSIPHY0_CLK>,
+				<&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,
+				<&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
+				<&clock_camcc CAM_CC_CSIPHY1_CLK>,
+				<&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,
+				<&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
+				<&clock_camcc CAM_CC_CSIPHY2_CLK>,
+				<&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,
+				<&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
+				<&clock_camcc CAM_CC_CSIPHY3_CLK>,
+				<&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>,
+				<&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
+				<&gcc GCC_CAMERA_AHB_CLK>,
+				<&gcc GCC_CAMERA_AXI_CLK>,
+				<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
+				<&clock_camcc CAM_CC_SOC_AHB_CLK>,
+				<&clock_camcc CAM_CC_IFE_0_AXI_CLK>,
+				<&clock_camcc CAM_CC_IFE_0_CLK>,
+				<&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
+				<&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
+				<&clock_camcc CAM_CC_IFE_1_AXI_CLK>,
+				<&clock_camcc CAM_CC_IFE_1_CLK>,
+				<&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
+				<&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
+				<&clock_camcc CAM_CC_IFE_LITE_CLK>,
+				<&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+				<&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>;
+			clock-names = "camnoc_axi",
+				"cpas_ahb",
+				"cphy_rx_src",
+				"csi0",
+				"csi0_src",
+				"csi1",
+				"csi1_src",
+				"csi2",
+				"csi2_src",
+				"csiphy0",
+				"csiphy0_timer",
+				"csiphy0_timer_src",
+				"csiphy1",
+				"csiphy1_timer",
+				"csiphy1_timer_src",
+				"csiphy2",
+				"csiphy2_timer",
+				"csiphy2_timer_src",
+				"csiphy3",
+				"csiphy3_timer",
+				"csiphy3_timer_src",
+				"gcc_camera_ahb",
+				"gcc_camera_axi",
+				"slow_ahb_src",
+				"soc_ahb",
+				"vfe0_axi",
+				"vfe0",
+				"vfe0_cphy_rx",
+				"vfe0_src",
+				"vfe1_axi",
+				"vfe1",
+				"vfe1_cphy_rx",
+				"vfe1_src",
+				"vfe_lite",
+				"vfe_lite_cphy_rx",
+				"vfe_lite_src";
+
+			iommus = <&apps_smmu 0x0808 0x0>,
+				 <&apps_smmu 0x0810 0x8>,
+				 <&apps_smmu 0x0c08 0x0>,
+				 <&apps_smmu 0x0c10 0x8>;
+
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+
 		cci: cci@ac4a000 {
 			compatible = "qcom,sdm845-cci";
 			#address-cells = <1>;