diff mbox series

[6/6] clk: qcom: gcc-sdm660: Add CLK_SET_RATE_PARENT where applicable

Message ID 20210220155618.176559-6-konrad.dybcio@somainline.org (mailing list archive)
State New
Headers show
Series [1/6] clk: qcom: gcc-sdm660: Fix hmss_gpll0_clk_src parent_map | expand

Commit Message

Konrad Dybcio Feb. 20, 2021, 3:56 p.m. UTC
Some branch clocks should explicitly set this flag to make sure
they inherit their frequencies from the parent clock.

Fixes: f2a76a2955c0 ("clk: qcom: Add Global Clock controller (GCC) driver for SDM660")
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
 drivers/clk/qcom/gcc-sdm660.c | 4 ++++
 1 file changed, 4 insertions(+)

Comments

Stephen Boyd Feb. 23, 2021, 12:42 a.m. UTC | #1
Quoting Konrad Dybcio (2021-02-20 07:56:17)
> Some branch clocks should explicitly set this flag to make sure
> they inherit their frequencies from the parent clock.

This flag doesn't have anything to do with inheriting the rate from the
parent.

> 
> Fixes: f2a76a2955c0 ("clk: qcom: Add Global Clock controller (GCC) driver for SDM660")
> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Konrad Dybcio Feb. 25, 2021, 7:27 p.m. UTC | #2
On 23.02.2021 01:42, Stephen Boyd wrote:
> Quoting Konrad Dybcio (2021-02-20 07:56:17)
>> Some branch clocks should explicitly set this flag to make sure
>> they inherit their frequencies from the parent clock.
> This flag doesn't have anything to do with inheriting the rate from the
> parent.
>
Right. "Some branch clocks should explicitly set this flag to make sure the frequency changes are propagated to their respective parents if need be." should sound better.


Konrad
diff mbox series

Patch

diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c
index db2185c88b77..2c182936fc09 100644
--- a/drivers/clk/qcom/gcc-sdm660.c
+++ b/drivers/clk/qcom/gcc-sdm660.c
@@ -1606,6 +1606,7 @@  static struct clk_branch gcc_gpu_gpll0_clk = {
 				"gpll0",
 			},
 			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
@@ -1623,6 +1624,7 @@  static struct clk_branch gcc_gpu_gpll0_div_clk = {
 				"gpll0_early_div",
 			},
 			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
@@ -1672,6 +1674,7 @@  static struct clk_branch gcc_mmss_gpll0_clk = {
 				"gpll0",
 			},
 			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
@@ -1689,6 +1692,7 @@  static struct clk_branch gcc_mmss_gpll0_div_clk = {
 				"gpll0_early_div",
 			},
 			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},