| Message ID | 20210224230143.1216118-1-dmitry.baryshkov@linaro.org (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 19f4a055abf2a69a1c0109456c3758b5697730c9 |
| Headers | show |
| Series | drm/msm/dsi_pll_7nm: Solve TODO for multiplier frac_bits assignment | expand |
Hi Dmitry Thanks for the patch. On 2021-02-24 15:01, Dmitry Baryshkov wrote: > The number of fractional registers bits is known and already set in > the frac_bits variable of the dsi_pll_config struct here in 7nm: > remove the TODO by simply using that variable. This is a copy of > 196145eb1af1 ("drm/msm/dsi_pll_10nm: Solve TODO for multiplier > frac_bits > assignment"). > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> > --- > drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c > b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c > index c1f6708367ae..0458eda15114 100644 > --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c > +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c > @@ -509,6 +509,7 @@ static unsigned long > dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw, > { > struct msm_dsi_pll *pll = hw_clk_to_pll(hw); > struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); > + struct dsi_pll_config *config = &pll_7nm->pll_configuration; > void __iomem *base = pll_7nm->mmio; > u64 ref_clk = pll_7nm->vco_ref_clk_rate; > u64 vco_rate = 0x0; > @@ -529,9 +530,8 @@ static unsigned long > dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw, > /* > * TODO: > * 1. Assumes prescaler is disabled > - * 2. Multiplier is 2^18. it should be 2^(num_of_frac_bits) > */ > - multiplier = 1 << 18; > + multiplier = 1 << config->frac_bits; > pll_freq = dec * (ref_clk * 2); > tmp64 = (ref_clk * 2 * frac); > pll_freq += div_u64(tmp64, multiplier);
Hello: This patch was applied to qcom/linux.git (refs/heads/for-next): On Thu, 25 Feb 2021 02:01:43 +0300 you wrote: > The number of fractional registers bits is known and already set in > the frac_bits variable of the dsi_pll_config struct here in 7nm: > remove the TODO by simply using that variable. This is a copy of > 196145eb1af1 ("drm/msm/dsi_pll_10nm: Solve TODO for multiplier frac_bits > assignment"). > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > [...] Here is the summary with links: - drm/msm/dsi_pll_7nm: Solve TODO for multiplier frac_bits assignment https://git.kernel.org/qcom/c/19f4a055abf2 You are awesome, thank you! -- Deet-doot-dot, I am a bot. https://korg.docs.kernel.org/patchwork/pwbot.html
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c index c1f6708367ae..0458eda15114 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c @@ -509,6 +509,7 @@ static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw, { struct msm_dsi_pll *pll = hw_clk_to_pll(hw); struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); + struct dsi_pll_config *config = &pll_7nm->pll_configuration; void __iomem *base = pll_7nm->mmio; u64 ref_clk = pll_7nm->vco_ref_clk_rate; u64 vco_rate = 0x0; @@ -529,9 +530,8 @@ static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw, /* * TODO: * 1. Assumes prescaler is disabled - * 2. Multiplier is 2^18. it should be 2^(num_of_frac_bits) */ - multiplier = 1 << 18; + multiplier = 1 << config->frac_bits; pll_freq = dec * (ref_clk * 2); tmp64 = (ref_clk * 2 * frac); pll_freq += div_u64(tmp64, multiplier);
The number of fractional registers bits is known and already set in the frac_bits variable of the dsi_pll_config struct here in 7nm: remove the TODO by simply using that variable. This is a copy of 196145eb1af1 ("drm/msm/dsi_pll_10nm: Solve TODO for multiplier frac_bits assignment"). Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)