| Message ID | 20210224230528.1216677-1-dmitry.baryshkov@linaro.org (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 9daaf31307856defb1070685418ce5a484ecda3a |
| Headers | show |
| Series | drm/msm/dsi_pll_7nm: Fix variable usage for pll_lockdet_rate | expand |
Hi Dmitry Thanks for the patch. On 2021-02-24 15:05, Dmitry Baryshkov wrote: > The PLL_LOCKDET_RATE_1 was being programmed with a hardcoded value > directly, but the same value was also being specified in the > dsi_pll_regs struct pll_lockdet_rate variable: let's use it! > > Based on 362cadf34b9f ("drm/msm/dsi_pll_10nm: Fix variable usage for > pll_lockdet_rate") > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> > --- > drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c > b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c > index 0458eda15114..e29b3bfd63d1 100644 > --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c > +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c > @@ -325,7 +325,7 @@ static void dsi_pll_commit(struct dsi_pll_7nm *pll) > pll_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1, > reg->frac_div_start_low); > pll_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1, > reg->frac_div_start_mid); > pll_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1, > reg->frac_div_start_high); > - pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1, 0x40); > + pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1, > reg->pll_lockdet_rate); > pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY, 0x06); > pll_write(base + REG_DSI_7nm_PHY_PLL_CMODE_1, 0x10); /* TODO: 0x00 > for CPHY */ > pll_write(base + REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS, > reg->pll_clock_inverters);
Hello: This patch was applied to qcom/linux.git (refs/heads/for-next): On Thu, 25 Feb 2021 02:05:28 +0300 you wrote: > The PLL_LOCKDET_RATE_1 was being programmed with a hardcoded value > directly, but the same value was also being specified in the > dsi_pll_regs struct pll_lockdet_rate variable: let's use it! > > Based on 362cadf34b9f ("drm/msm/dsi_pll_10nm: Fix variable usage for > pll_lockdet_rate") > > [...] Here is the summary with links: - drm/msm/dsi_pll_7nm: Fix variable usage for pll_lockdet_rate https://git.kernel.org/qcom/c/9daaf3130785 You are awesome, thank you! -- Deet-doot-dot, I am a bot. https://korg.docs.kernel.org/patchwork/pwbot.html
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c index 0458eda15114..e29b3bfd63d1 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c @@ -325,7 +325,7 @@ static void dsi_pll_commit(struct dsi_pll_7nm *pll) pll_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1, reg->frac_div_start_low); pll_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1, reg->frac_div_start_mid); pll_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1, reg->frac_div_start_high); - pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1, 0x40); + pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1, reg->pll_lockdet_rate); pll_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY, 0x06); pll_write(base + REG_DSI_7nm_PHY_PLL_CMODE_1, 0x10); /* TODO: 0x00 for CPHY */ pll_write(base + REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS, reg->pll_clock_inverters);
The PLL_LOCKDET_RATE_1 was being programmed with a hardcoded value directly, but the same value was also being specified in the dsi_pll_regs struct pll_lockdet_rate variable: let's use it! Based on 362cadf34b9f ("drm/msm/dsi_pll_10nm: Fix variable usage for pll_lockdet_rate") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)