[v2,09/28] drm/msm/dsi: move min/max PLL rate to phy config

Message ID	20210324151846.2774204-10-dmitry.baryshkov@linaro.org (mailing list archive)
State	Not Applicable, archived
Headers	show Return-Path: <linux-arm-msm-owner@kernel.org> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> To: Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>, Jonathan Marek <jonathan@marek.ca>, Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org>, David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org Subject: [PATCH v2 09/28] drm/msm/dsi: move min/max PLL rate to phy config Date: Wed, 24 Mar 2021 18:18:27 +0300 Message-Id: <20210324151846.2774204-10-dmitry.baryshkov@linaro.org> In-Reply-To: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> References: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	[v2,01/28] clk: fixed: add devm helper for clk_hw_register_fixed_factor() \| expand [v2,01/28] clk: fixed: add devm helper for clk_hw_register_fixed_factor() [v2,02/28] clk: mux: provide devm_clk_hw_register_mux() [v2,03/28] clk: divider: add devm_clk_hw_register_divider [v2,04/28] drm/msm/dsi: replace PHY's init callback with configurable data [v2,06/28] drm/msm/dsi: drop multiple pll enable_seq support [v2,07/28] drm/msm/dsi: move all PLL callbacks into PHY config struct [v2,08/28] drm/msm/dsi: drop global msm_dsi_phy_type enumaration [v2,09/28] drm/msm/dsi: move min/max PLL rate to phy config [v2,10/28] drm/msm/dsi: remove msm_dsi_pll_set_usecase [v2,11/28] drm/msm/dsi: stop setting clock parents manually [v2,12/28] arm64: dts: qcom: sdm845: assign DSI clock source parents [v2,13/28] arm64: dts: qcom: sc7180: assign DSI clock source parents [v2,14/28] drm/msm/dsi: push provided clocks handling into a generic code [v2,15/28] drm/msm/dsi: use devm_clk_*register to registe DSI PHY clocks [v2,16/28] drm/msm/dsi: use devm_of_clk_add_hw_provider [v2,17/28] drm/msm/dsi: make save/restore_state phy-level functions [v2,18/28] drm/msm/dsi: drop vco_delay setting from 7nm, 10nm, 14nm drivers [v2,19/28] drm/msm/dpu: simplify vco_delay handling in dsi_phy_28nm driver [v2,20/28] drm/msi/dsi: inline msm_dsi_pll_helper_clk_prepare/unprepare [v2,21/28] drm/msm/dsi: make save_state/restore_state callbacks accept msm_dsi_phy [v2,22/28] drm/msm/dsi: drop msm_dsi_pll abstracton [v2,23/28] drm/msm/dsi: drop PLL accessor functions [v2,24/28] drm/msm/dsi: move ioremaps to dsi_phy_driver_probe [v2,25/28] drm/msm/dsi: remove duplicate fields from dsi_pll_Nnm instances [v2,26/28] drm/msm/dsi: remove temp data from global pll structure [v2,27/28] drm/msm/dsi: inline msm_dsi_phy_set_src_pll [v2,28/28] drm/msm/dsi: stop passing src_pll_id to the phy_enable call

Message ID

20210324151846.2774204-10-dmitry.baryshkov@linaro.org (mailing list archive)

State

Not Applicable, archived

Headers

From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>,
        Jonathan Marek <jonathan@marek.ca>,
        Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>, David Airlie <airlied@linux.ie>,
        Daniel Vetter <daniel@ffwll.ch>, linux-arm-msm@vger.kernel.org,
        dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org,
        linux-clk@vger.kernel.org
Subject: [PATCH v2 09/28] drm/msm/dsi: move min/max PLL rate to phy config
Date: Wed, 24 Mar 2021 18:18:27 +0300
Message-Id: <20210324151846.2774204-10-dmitry.baryshkov@linaro.org>
In-Reply-To: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org>
References: <20210324151846.2774204-1-dmitry.baryshkov@linaro.org>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Precedence: bulk

Series

[v2,01/28] clk: fixed: add devm helper for clk_hw_register_fixed_factor() | expand

Commit Message

Dmitry Baryshkov March 24, 2021, 3:18 p.m. UTC

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.h           |  3 +++
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c      |  6 ++++--
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c      |  6 ++++--
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c      |  8 ++++++--
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c |  4 ++--
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c       | 12 ++++--------
 drivers/gpu/drm/msm/dsi/phy/dsi_pll.c           |  8 ++++----
 drivers/gpu/drm/msm/dsi/phy/dsi_pll.h           |  3 ---
 8 files changed, 27 insertions(+), 23 deletions(-)

Comments

Abhinav Kumar March 26, 2021, 5:53 p.m. UTC | #1

On 2021-03-24 08:18, Dmitry Baryshkov wrote:
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/dsi/phy/dsi_phy.h           |  3 +++
>  drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c      |  6 ++++--
>  drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c      |  6 ++++--
>  drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c      |  8 ++++++--
>  drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c |  4 ++--
>  drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c       | 12 ++++--------
>  drivers/gpu/drm/msm/dsi/phy/dsi_pll.c           |  8 ++++----
>  drivers/gpu/drm/msm/dsi/phy/dsi_pll.h           |  3 ---
>  8 files changed, 27 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> index 39abb86446f9..000e4207dabc 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> @@ -38,6 +38,9 @@ struct msm_dsi_phy_cfg {
>  	struct msm_dsi_phy_ops ops;
>  	const struct msm_dsi_pll_ops pll_ops;
> 
> +	unsigned long	min_pll_rate;
> +	unsigned long	max_pll_rate;
> +
>  	/*
>  	 * Each cell {phy_id, pll_id} of the truth table indicates
>  	 * if the source PLL selection bit should be set for each PHY.
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> index dc8ccc994759..5f9d0cfc4e03 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> @@ -864,8 +864,6 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy 
> *phy)
>  	spin_lock_init(&pll_10nm->postdiv_lock);
> 
>  	pll = &pll_10nm->base;
> -	pll->min_rate = 1000000000UL;
> -	pll->max_rate = 3500000000UL;
>  	pll->cfg = phy->cfg;
> 
>  	pll_10nm->vco_delay = 1;
> @@ -1113,6 +1111,8 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = 
> {
>  		.restore_state = dsi_pll_10nm_restore_state,
>  		.set_usecase = dsi_pll_10nm_set_usecase,
>  	},
> +	.min_pll_rate = 1000000000UL,
> +	.max_pll_rate = 3500000000UL,
>  	.io_start = { 0xae94400, 0xae96400 },
>  	.num_dsi_phy = 2,
>  };
> @@ -1138,6 +1138,8 @@ const struct msm_dsi_phy_cfg 
> dsi_phy_10nm_8998_cfgs = {
>  		.restore_state = dsi_pll_10nm_restore_state,
>  		.set_usecase = dsi_pll_10nm_set_usecase,
>  	},
> +	.min_pll_rate = 1000000000UL,
> +	.max_pll_rate = 3500000000UL,
>  	.io_start = { 0xc994400, 0xc996400 },
>  	.num_dsi_phy = 2,
>  	.quirks = DSI_PHY_10NM_QUIRK_OLD_TIMINGS,
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> index d78f846cf8e4..8e4528301e5d 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> @@ -1078,8 +1078,6 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy 
> *phy)
>  	spin_lock_init(&pll_14nm->postdiv_lock);
> 
>  	pll = &pll_14nm->base;
> -	pll->min_rate = VCO_MIN_RATE;
> -	pll->max_rate = VCO_MAX_RATE;
>  	pll->cfg = phy->cfg;
> 
>  	pll_14nm->vco_delay = 1;
> @@ -1237,6 +1235,8 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = 
> {
>  		.disable_seq = dsi_pll_14nm_disable_seq,
>  		.enable_seq = dsi_pll_14nm_enable_seq,
>  	},
> +	.min_pll_rate = VCO_MIN_RATE,
> +	.max_pll_rate = VCO_MAX_RATE,
>  	.io_start = { 0x994400, 0x996400 },
>  	.num_dsi_phy = 2,
>  };
> @@ -1264,6 +1264,8 @@ const struct msm_dsi_phy_cfg 
> dsi_phy_14nm_660_cfgs = {
>  		.disable_seq = dsi_pll_14nm_disable_seq,
>  		.enable_seq = dsi_pll_14nm_enable_seq,
>  	},
> +	.min_pll_rate = VCO_MIN_RATE,
> +	.max_pll_rate = VCO_MAX_RATE,
>  	.io_start = { 0xc994400, 0xc996000 },
>  	.num_dsi_phy = 2,
>  };
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> index bb33261d606d..d267b25e5da0 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> @@ -625,8 +625,6 @@ static int dsi_pll_28nm_init(struct msm_dsi_phy 
> *phy)
>  	}
> 
>  	pll = &pll_28nm->base;
> -	pll->min_rate = VCO_MIN_RATE;
> -	pll->max_rate = VCO_MAX_RATE;
>  	if (phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
>  		pll_28nm->vco_delay = 1000;
>  	else
> @@ -811,6 +809,8 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs 
> = {
>  		.disable_seq = dsi_pll_28nm_disable_seq,
>  		.enable_seq = dsi_pll_28nm_enable_seq_hpm,
>  	},
> +	.min_pll_rate = VCO_MIN_RATE,
> +	.max_pll_rate = VCO_MAX_RATE,
>  	.io_start = { 0xfd922b00, 0xfd923100 },
>  	.num_dsi_phy = 2,
>  };
> @@ -837,6 +837,8 @@ const struct msm_dsi_phy_cfg 
> dsi_phy_28nm_hpm_famb_cfgs = {
>  		.disable_seq = dsi_pll_28nm_disable_seq,
>  		.enable_seq = dsi_pll_28nm_enable_seq_hpm,
>  	},
> +	.min_pll_rate = VCO_MIN_RATE,
> +	.max_pll_rate = VCO_MAX_RATE,
>  	.io_start = { 0x1a94400, 0x1a96400 },
>  	.num_dsi_phy = 2,
>  };
> @@ -863,6 +865,8 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = 
> {
>  		.disable_seq = dsi_pll_28nm_disable_seq,
>  		.enable_seq = dsi_pll_28nm_enable_seq_lp,
>  	},
> +	.min_pll_rate = VCO_MIN_RATE,
> +	.max_pll_rate = VCO_MAX_RATE,
>  	.io_start = { 0x1a98500 },
>  	.num_dsi_phy = 1,
>  	.quirks = DSI_PHY_28NM_QUIRK_PHY_LP,
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> index 79b0842a8dc4..31e7910c6050 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
> @@ -508,8 +508,6 @@ static int dsi_pll_28nm_8960_init(struct 
> msm_dsi_phy *phy)
>  	}
> 
>  	pll = &pll_28nm->base;
> -	pll->min_rate = VCO_MIN_RATE;
> -	pll->max_rate = VCO_MAX_RATE;
> 
>  	pll->cfg = phy->cfg;
> 
> @@ -711,6 +709,8 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs 
> = {
>  		.disable_seq = dsi_pll_28nm_disable_seq,
>  		.enable_seq = dsi_pll_28nm_enable_seq,
>  	},
> +	.min_pll_rate = VCO_MIN_RATE,
> +	.max_pll_rate = VCO_MAX_RATE,
>  	.io_start = { 0x4700300, 0x5800300 },
>  	.num_dsi_phy = 2,
>  };
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> index 44ae495e8fca..4831d6769da7 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> @@ -889,14 +889,6 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy 
> *phy)
>  	spin_lock_init(&pll_7nm->postdiv_lock);
> 
>  	pll = &pll_7nm->base;
> -	pll->min_rate = 1000000000UL;
> -	pll->max_rate = 3500000000UL;
> -	if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
> -		pll->min_rate = 600000000UL;
> -		pll->max_rate = (unsigned long)5000000000ULL;
> -		/* workaround for max rate overflowing on 32-bit builds: */
> -		pll->max_rate = max(pll->max_rate, 0xffffffffUL);
> -	}
>  	pll->cfg = phy->cfg;
> 
>  	pll_7nm->vco_delay = 1;
> @@ -1152,6 +1144,8 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
>  		.restore_state = dsi_pll_7nm_restore_state,
>  		.set_usecase = dsi_pll_7nm_set_usecase,
>  	},
> +	.min_pll_rate = 600000000UL,
> +	.max_pll_rate = (5000000000ULL < ULONG_MAX) ? 5000000000ULL : 
> ULONG_MAX,
>  	.io_start = { 0xae94400, 0xae96400 },
>  	.num_dsi_phy = 2,
>  	.quirks = DSI_PHY_7NM_QUIRK_V4_1,
> @@ -1178,6 +1172,8 @@ const struct msm_dsi_phy_cfg 
> dsi_phy_7nm_8150_cfgs = {
>  		.restore_state = dsi_pll_7nm_restore_state,
>  		.set_usecase = dsi_pll_7nm_set_usecase,
>  	},
> +	.min_pll_rate = 1000000000UL,
> +	.max_pll_rate = 3500000000UL,
>  	.io_start = { 0xae94400, 0xae96400 },
>  	.num_dsi_phy = 2,
>  };
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
> index c7ff0eba0e8b..e607adffe001 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
> @@ -14,10 +14,10 @@ long msm_dsi_pll_helper_clk_round_rate(struct 
> clk_hw *hw,
>  {
>  	struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
> 
> -	if      (rate < pll->min_rate)
> -		return  pll->min_rate;
> -	else if (rate > pll->max_rate)
> -		return  pll->max_rate;
> +	if      (rate < pll->cfg->min_pll_rate)
> +		return  pll->cfg->min_pll_rate;
> +	else if (rate > pll->cfg->max_pll_rate)
> +		return  pll->cfg->max_pll_rate;
>  	else
>  		return rate;
>  }
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
> b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
> index 4fa73fbcba52..8306911f8318 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
> @@ -18,9 +18,6 @@ struct msm_dsi_pll {
>  	bool		pll_on;
>  	bool		state_saved;
> 
> -	unsigned long	min_rate;
> -	unsigned long	max_rate;
> -
>  	const struct msm_dsi_phy_cfg *cfg;
>  };

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index 39abb86446f9..000e4207dabc 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -38,6 +38,9 @@  struct msm_dsi_phy_cfg {
 	struct msm_dsi_phy_ops ops;
 	const struct msm_dsi_pll_ops pll_ops;
 
+	unsigned long	min_pll_rate;
+	unsigned long	max_pll_rate;
+
 	/*
 	 * Each cell {phy_id, pll_id} of the truth table indicates
 	 * if the source PLL selection bit should be set for each PHY.
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
index dc8ccc994759..5f9d0cfc4e03 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
@@ -864,8 +864,6 @@  static int dsi_pll_10nm_init(struct msm_dsi_phy *phy)
 	spin_lock_init(&pll_10nm->postdiv_lock);
 
 	pll = &pll_10nm->base;
-	pll->min_rate = 1000000000UL;
-	pll->max_rate = 3500000000UL;
 	pll->cfg = phy->cfg;
 
 	pll_10nm->vco_delay = 1;
@@ -1113,6 +1111,8 @@  const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = {
 		.restore_state = dsi_pll_10nm_restore_state,
 		.set_usecase = dsi_pll_10nm_set_usecase,
 	},
+	.min_pll_rate = 1000000000UL,
+	.max_pll_rate = 3500000000UL,
 	.io_start = { 0xae94400, 0xae96400 },
 	.num_dsi_phy = 2,
 };
@@ -1138,6 +1138,8 @@  const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = {
 		.restore_state = dsi_pll_10nm_restore_state,
 		.set_usecase = dsi_pll_10nm_set_usecase,
 	},
+	.min_pll_rate = 1000000000UL,
+	.max_pll_rate = 3500000000UL,
 	.io_start = { 0xc994400, 0xc996400 },
 	.num_dsi_phy = 2,
 	.quirks = DSI_PHY_10NM_QUIRK_OLD_TIMINGS,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
index d78f846cf8e4..8e4528301e5d 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
@@ -1078,8 +1078,6 @@  static int dsi_pll_14nm_init(struct msm_dsi_phy *phy)
 	spin_lock_init(&pll_14nm->postdiv_lock);
 
 	pll = &pll_14nm->base;
-	pll->min_rate = VCO_MIN_RATE;
-	pll->max_rate = VCO_MAX_RATE;
 	pll->cfg = phy->cfg;
 
 	pll_14nm->vco_delay = 1;
@@ -1237,6 +1235,8 @@  const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {
 		.disable_seq = dsi_pll_14nm_disable_seq,
 		.enable_seq = dsi_pll_14nm_enable_seq,
 	},
+	.min_pll_rate = VCO_MIN_RATE,
+	.max_pll_rate = VCO_MAX_RATE,
 	.io_start = { 0x994400, 0x996400 },
 	.num_dsi_phy = 2,
 };
@@ -1264,6 +1264,8 @@  const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = {
 		.disable_seq = dsi_pll_14nm_disable_seq,
 		.enable_seq = dsi_pll_14nm_enable_seq,
 	},
+	.min_pll_rate = VCO_MIN_RATE,
+	.max_pll_rate = VCO_MAX_RATE,
 	.io_start = { 0xc994400, 0xc996000 },
 	.num_dsi_phy = 2,
 };
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
index bb33261d606d..d267b25e5da0 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
@@ -625,8 +625,6 @@  static int dsi_pll_28nm_init(struct msm_dsi_phy *phy)
 	}
 
 	pll = &pll_28nm->base;
-	pll->min_rate = VCO_MIN_RATE;
-	pll->max_rate = VCO_MAX_RATE;
 	if (phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
 		pll_28nm->vco_delay = 1000;
 	else
@@ -811,6 +809,8 @@  const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = {
 		.disable_seq = dsi_pll_28nm_disable_seq,
 		.enable_seq = dsi_pll_28nm_enable_seq_hpm,
 	},
+	.min_pll_rate = VCO_MIN_RATE,
+	.max_pll_rate = VCO_MAX_RATE,
 	.io_start = { 0xfd922b00, 0xfd923100 },
 	.num_dsi_phy = 2,
 };
@@ -837,6 +837,8 @@  const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = {
 		.disable_seq = dsi_pll_28nm_disable_seq,
 		.enable_seq = dsi_pll_28nm_enable_seq_hpm,
 	},
+	.min_pll_rate = VCO_MIN_RATE,
+	.max_pll_rate = VCO_MAX_RATE,
 	.io_start = { 0x1a94400, 0x1a96400 },
 	.num_dsi_phy = 2,
 };
@@ -863,6 +865,8 @@  const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = {
 		.disable_seq = dsi_pll_28nm_disable_seq,
 		.enable_seq = dsi_pll_28nm_enable_seq_lp,
 	},
+	.min_pll_rate = VCO_MIN_RATE,
+	.max_pll_rate = VCO_MAX_RATE,
 	.io_start = { 0x1a98500 },
 	.num_dsi_phy = 1,
 	.quirks = DSI_PHY_28NM_QUIRK_PHY_LP,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
index 79b0842a8dc4..31e7910c6050 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
@@ -508,8 +508,6 @@  static int dsi_pll_28nm_8960_init(struct msm_dsi_phy *phy)
 	}
 
 	pll = &pll_28nm->base;
-	pll->min_rate = VCO_MIN_RATE;
-	pll->max_rate = VCO_MAX_RATE;
 
 	pll->cfg = phy->cfg;
 
@@ -711,6 +709,8 @@  const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = {
 		.disable_seq = dsi_pll_28nm_disable_seq,
 		.enable_seq = dsi_pll_28nm_enable_seq,
 	},
+	.min_pll_rate = VCO_MIN_RATE,
+	.max_pll_rate = VCO_MAX_RATE,
 	.io_start = { 0x4700300, 0x5800300 },
 	.num_dsi_phy = 2,
 };
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index 44ae495e8fca..4831d6769da7 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -889,14 +889,6 @@  static int dsi_pll_7nm_init(struct msm_dsi_phy *phy)
 	spin_lock_init(&pll_7nm->postdiv_lock);
 
 	pll = &pll_7nm->base;
-	pll->min_rate = 1000000000UL;
-	pll->max_rate = 3500000000UL;
-	if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
-		pll->min_rate = 600000000UL;
-		pll->max_rate = (unsigned long)5000000000ULL;
-		/* workaround for max rate overflowing on 32-bit builds: */
-		pll->max_rate = max(pll->max_rate, 0xffffffffUL);
-	}
 	pll->cfg = phy->cfg;
 
 	pll_7nm->vco_delay = 1;
@@ -1152,6 +1144,8 @@  const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
 		.restore_state = dsi_pll_7nm_restore_state,
 		.set_usecase = dsi_pll_7nm_set_usecase,
 	},
+	.min_pll_rate = 600000000UL,
+	.max_pll_rate = (5000000000ULL < ULONG_MAX) ? 5000000000ULL : ULONG_MAX,
 	.io_start = { 0xae94400, 0xae96400 },
 	.num_dsi_phy = 2,
 	.quirks = DSI_PHY_7NM_QUIRK_V4_1,
@@ -1178,6 +1172,8 @@  const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = {
 		.restore_state = dsi_pll_7nm_restore_state,
 		.set_usecase = dsi_pll_7nm_set_usecase,
 	},
+	.min_pll_rate = 1000000000UL,
+	.max_pll_rate = 3500000000UL,
 	.io_start = { 0xae94400, 0xae96400 },
 	.num_dsi_phy = 2,
 };
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
index c7ff0eba0e8b..e607adffe001 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
@@ -14,10 +14,10 @@  long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw,
 {
 	struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
 
-	if      (rate < pll->min_rate)
-		return  pll->min_rate;
-	else if (rate > pll->max_rate)
-		return  pll->max_rate;
+	if      (rate < pll->cfg->min_pll_rate)
+		return  pll->cfg->min_pll_rate;
+	else if (rate > pll->cfg->max_pll_rate)
+		return  pll->cfg->max_pll_rate;
 	else
 		return rate;
 }
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
index 4fa73fbcba52..8306911f8318 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
@@ -18,9 +18,6 @@  struct msm_dsi_pll {
 	bool		pll_on;
 	bool		state_saved;
 
-	unsigned long	min_rate;
-	unsigned long	max_rate;
-
 	const struct msm_dsi_phy_cfg *cfg;
 };

[v2,09/28] drm/msm/dsi: move min/max PLL rate to phy config

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