diff mbox series

[v2,3/3] drm/msm/dpu: hw_blk: make dpu_hw_blk empty opaque structure

Message ID 20210422130804.825030-4-dmitry.baryshkov@linaro.org (mailing list archive)
State Superseded
Headers show
Series drm/msm/dpu: simplify dpu_hw_blk handling | expand

Commit Message

Dmitry Baryshkov April 22, 2021, 1:08 p.m. UTC 
The code does not really use dpu_hw_blk fields, so drop them, making
dpu_hw_blk empty structure.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/Makefile                  |  1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c    | 24 -------------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h    |  4 +---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c    |  2 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c   |  2 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c   |  2 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c     |  2 --
 .../gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c    |  2 --
 .../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c   |  2 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c   |  2 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c    |  2 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c        |  2 +-
 12 files changed, 2 insertions(+), 45 deletions(-)
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c

Comments

kernel test robot April 22, 2021, 5:08 p.m. UTC | #1 
Hi Dmitry,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on next-20210422]
[also build test ERROR on v5.12-rc8]
[cannot apply to linus/master v5.12-rc8 v5.12-rc7 v5.12-rc6]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Dmitry-Baryshkov/drm-msm-dpu-simplify-dpu_hw_blk-handling/20210422-211129
base:    c457d9676496f5a895509f9c510278beaaffc829
config: arm-defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/c023ff88d40d423b82b71cd504d787049dcd2046
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Dmitry-Baryshkov/drm-msm-dpu-simplify-dpu_hw_blk-handling/20210422-211129
        git checkout c023ff88d40d423b82b71cd504d787049dcd2046
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross W=1 ARCH=arm 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

   drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c: In function 'dpu_encoder_phys_vid_setup_timing_engine':
>> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c:287:48: error: 'struct dpu_hw_blk' has no member named 'id'
     287 |   intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->id;
         |                                                ^~
   drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c: In function 'dpu_encoder_phys_vid_enable':
   drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c:464:72: error: 'struct dpu_hw_blk' has no member named 'id'
     464 |   ctl->ops.update_pending_flush_merge_3d(ctl, phys_enc->hw_pp->merge_3d->id);
         |                                                                        ^~


vim +287 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c

25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  239  
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  240  static void dpu_encoder_phys_vid_setup_timing_engine(
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  241  		struct dpu_encoder_phys *phys_enc)
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  242  {
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  243  	struct drm_display_mode mode;
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  244  	struct intf_timing_params timing_params = { 0 };
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  245  	const struct dpu_format *fmt = NULL;
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  246  	u32 fmt_fourcc = DRM_FORMAT_RGB888;
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  247  	unsigned long lock_flags;
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  248  	struct dpu_hw_intf_cfg intf_cfg = { 0 };
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  249  
5e7d4a8407d37a Drew Davenport    2019-12-06  250  	if (!phys_enc->hw_ctl->ops.setup_intf_cfg) {
30801221a73781 Zheng Bin         2020-01-23  251  		DPU_ERROR("invalid encoder %d\n", phys_enc != NULL);
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  252  		return;
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  253  	}
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  254  
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  255  	mode = phys_enc->cached_mode;
b6057cda8f6cac Jeykumar Sankaran 2019-02-13  256  	if (!phys_enc->hw_intf->ops.setup_timing_gen) {
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  257  		DPU_ERROR("timing engine setup is not supported\n");
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  258  		return;
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  259  	}
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  260  
b6057cda8f6cac Jeykumar Sankaran 2019-02-13  261  	DPU_DEBUG_VIDENC(phys_enc, "enabling mode:\n");
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  262  	drm_mode_debug_printmodeline(&mode);
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  263  
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  264  	if (phys_enc->split_role != ENC_ROLE_SOLO) {
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  265  		mode.hdisplay >>= 1;
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  266  		mode.htotal >>= 1;
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  267  		mode.hsync_start >>= 1;
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  268  		mode.hsync_end >>= 1;
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  269  
b6057cda8f6cac Jeykumar Sankaran 2019-02-13  270  		DPU_DEBUG_VIDENC(phys_enc,
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  271  			"split_role %d, halve horizontal %d %d %d %d\n",
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  272  			phys_enc->split_role,
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  273  			mode.hdisplay, mode.htotal,
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  274  			mode.hsync_start, mode.hsync_end);
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  275  	}
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  276  
b6057cda8f6cac Jeykumar Sankaran 2019-02-13  277  	drm_mode_to_intf_timing_params(phys_enc, &mode, &timing_params);
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  278  
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  279  	fmt = dpu_get_dpu_format(fmt_fourcc);
b6057cda8f6cac Jeykumar Sankaran 2019-02-13  280  	DPU_DEBUG_VIDENC(phys_enc, "fmt_fourcc 0x%X\n", fmt_fourcc);
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  281  
b6057cda8f6cac Jeykumar Sankaran 2019-02-13  282  	intf_cfg.intf = phys_enc->hw_intf->idx;
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  283  	intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_VID;
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  284  	intf_cfg.stream_sel = 0; /* Don't care value for video mode */
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  285  	intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
3e79527a33a83b Dmitry Baryshkov  2020-10-22  286  	if (phys_enc->hw_pp->merge_3d)
3e79527a33a83b Dmitry Baryshkov  2020-10-22 @287  		intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->id;
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  288  
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  289  	spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
b6057cda8f6cac Jeykumar Sankaran 2019-02-13  290  	phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf,
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  291  			&timing_params, fmt);
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  292  	phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);
73bfb790ac786c Kalyan Thota      2019-11-25  293  
73bfb790ac786c Kalyan Thota      2019-11-25  294  	/* setup which pp blk will connect to this intf */
73bfb790ac786c Kalyan Thota      2019-11-25  295  	if (phys_enc->hw_intf->ops.bind_pingpong_blk)
73bfb790ac786c Kalyan Thota      2019-11-25  296  		phys_enc->hw_intf->ops.bind_pingpong_blk(
73bfb790ac786c Kalyan Thota      2019-11-25  297  				phys_enc->hw_intf,
73bfb790ac786c Kalyan Thota      2019-11-25  298  				true,
73bfb790ac786c Kalyan Thota      2019-11-25  299  				phys_enc->hw_pp->idx);
73bfb790ac786c Kalyan Thota      2019-11-25  300  
3e79527a33a83b Dmitry Baryshkov  2020-10-22  301  	if (phys_enc->hw_pp->merge_3d) {
3e79527a33a83b Dmitry Baryshkov  2020-10-22  302  		struct dpu_hw_merge_3d *merge_3d = to_dpu_hw_merge_3d(phys_enc->hw_pp->merge_3d);
3e79527a33a83b Dmitry Baryshkov  2020-10-22  303  
3e79527a33a83b Dmitry Baryshkov  2020-10-22  304  		merge_3d->ops.setup_3d_mode(merge_3d, intf_cfg.mode_3d);
3e79527a33a83b Dmitry Baryshkov  2020-10-22  305  	}
3e79527a33a83b Dmitry Baryshkov  2020-10-22  306  
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  307  	spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  308  
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  309  	programmable_fetch_config(phys_enc, &timing_params);
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  310  }
25fdd5933e4c0f Jeykumar Sankaran 2018-06-27  311  

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
diff mbox series

Patch

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 610d630326bb..55dbde30c2a2 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -58,7 +58,6 @@  msm-y := \
 	disp/dpu1/dpu_encoder_phys_cmd.o \
 	disp/dpu1/dpu_encoder_phys_vid.o \
 	disp/dpu1/dpu_formats.o \
-	disp/dpu1/dpu_hw_blk.o \
 	disp/dpu1/dpu_hw_catalog.o \
 	disp/dpu1/dpu_hw_ctl.o \
 	disp/dpu1/dpu_hw_interrupts.o \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c
deleted file mode 100644
index 1f2b74b9eb65..000000000000
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c
+++ /dev/null
@@ -1,24 +0,0 @@ 
-// SPDX-License-Identifier: GPL-2.0-only
-/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
- */
-
-#define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__
-
-#include <linux/mutex.h>
-#include <linux/errno.h>
-#include <linux/slab.h>
-
-#include "dpu_hw_mdss.h"
-#include "dpu_hw_blk.h"
-
-/**
- * dpu_hw_blk_init - initialize hw block object
- * @hw_blk: pointer to hw block object
- * @type: hw block type - enum dpu_hw_blk_type
- * @id: instance id of the hw block
- */
-void dpu_hw_blk_init(struct dpu_hw_blk *hw_blk, u32 type, int id)
-{
-	hw_blk->type = type;
-	hw_blk->id = id;
-}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h
index 7768694b558a..52e92f37eda4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h
@@ -19,9 +19,7 @@  struct dpu_hw_blk;
  * @refcount: reference/usage count
  */
 struct dpu_hw_blk {
-	u32 type;
-	int id;
+	/* opaque */
 };
 
-void dpu_hw_blk_init(struct dpu_hw_blk *hw_blk, u32 type, int id);
 #endif /*_DPU_HW_BLK_H */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 441f66a4fb37..f8a74f6cdc4c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -613,8 +613,6 @@  struct dpu_hw_ctl *dpu_hw_ctl_init(enum dpu_ctl idx,
 	c->mixer_count = m->mixer_count;
 	c->mixer_hw_caps = m->mixer;
 
-	dpu_hw_blk_init(&c->base, DPU_HW_BLK_CTL, idx);
-
 	return c;
 }
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
index 977b25968f34..a98e964c3b6f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
@@ -110,8 +110,6 @@  struct dpu_hw_dspp *dpu_hw_dspp_init(enum dpu_dspp idx,
 	c->cap = cfg;
 	_setup_dspp_ops(c, c->cap->features);
 
-	dpu_hw_blk_init(&c->base, DPU_HW_BLK_DSPP, idx);
-
 	return c;
 }
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 17224556d5a8..116e2b5b1a90 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -325,8 +325,6 @@  struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx,
 	c->mdss = m;
 	_setup_intf_ops(&c->ops, c->cap->features);
 
-	dpu_hw_blk_init(&c->base, DPU_HW_BLK_INTF, idx);
-
 	return c;
 }
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
index 76f8b8f75b82..cb6bb7a22c15 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
@@ -182,8 +182,6 @@  struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx,
 	c->cap = cfg;
 	_setup_mixer_ops(m, &c->ops, c->cap->features);
 
-	dpu_hw_blk_init(&c->base, DPU_HW_BLK_LM, idx);
-
 	return c;
 }
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c
index 406ba950a066..c06d595d5df0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c
@@ -79,8 +79,6 @@  struct dpu_hw_merge_3d *dpu_hw_merge_3d_init(enum dpu_merge_3d idx,
 	c->caps = cfg;
 	_setup_merge_3d_ops(c, c->caps->features);
 
-	dpu_hw_blk_init(&c->base, DPU_HW_BLK_MERGE_3D, idx);
-
 	return c;
 }
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
index 92cd724263ce..55766c97c4c8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
@@ -282,8 +282,6 @@  struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx,
 	c->caps = cfg;
 	_setup_pingpong_ops(c, c->caps->features);
 
-	dpu_hw_blk_init(&c->base, DPU_HW_BLK_PINGPONG, idx);
-
 	return c;
 }
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index 8734a47040aa..69eed7932486 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -733,8 +733,6 @@  struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx,
 	hw_pipe->cap = cfg;
 	_setup_layer_ops(hw_pipe, hw_pipe->cap->features);
 
-	dpu_hw_blk_init(&hw_pipe->base, DPU_HW_BLK_SSPP, idx);
-
 	return hw_pipe;
 }
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
index dae77d9c2c74..282e3c6c6d48 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
@@ -322,8 +322,6 @@  struct dpu_hw_mdp *dpu_hw_mdptop_init(enum dpu_mdp idx,
 	mdp->caps = cfg;
 	_setup_mdp_ops(&mdp->ops, mdp->caps->features);
 
-	dpu_hw_blk_init(&mdp->base, DPU_HW_BLK_TOP, idx);
-
 	return mdp;
 }
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index fd2d104f0a91..5afdfceeaa6e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -428,7 +428,7 @@  static int _dpu_rm_reserve_ctls(
 		features = ctl->caps->features;
 		has_split_display = BIT(DPU_CTL_SPLIT_DISPLAY) & features;
 
-		DPU_DEBUG("ctl %d caps 0x%lX\n", rm->ctl_blks[j]->id, features);
+		DPU_DEBUG("ctl %d caps 0x%lX\n", j + CTL_0, features);
 
 		if (needs_split_display != has_split_display)
 			continue;