From patchwork Tue Apr 27 10:22:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenglin Wu X-Patchwork-Id: 12226051 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41F5CC43470 for ; Tue, 27 Apr 2021 10:24:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 13DC160FDC for ; Tue, 27 Apr 2021 10:24:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235459AbhD0KZP (ORCPT ); Tue, 27 Apr 2021 06:25:15 -0400 Received: from m43-7.mailgun.net ([69.72.43.7]:33596 "EHLO m43-7.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235369AbhD0KZO (ORCPT ); Tue, 27 Apr 2021 06:25:14 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1619519071; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=jWAUwABSHIxmfg4aBpPOjQbhhQgm6a1ARJ+qicZR39Y=; b=qREDc3y2dIv60XWswUwJGHHHl6pqSYXwpiS7CLtEi9T02Yvxibk9cGZsIp33iC8UXf423/3v gOKBZrFgBGmchirvK9ARlvF/T8S1/KlLpa8ENfhyPVesb3c9drwO8IEfrYsDKx2VawlBtXdh 95iY3oDmkqBxkrDU3ZaH57kt7Bw= X-Mailgun-Sending-Ip: 69.72.43.7 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n02.prod.us-west-2.postgun.com with SMTP id 6087e657215b831afb3e7bad (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Tue, 27 Apr 2021 10:24:23 GMT Sender: fenglinw=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id BCD77C43147; Tue, 27 Apr 2021 10:24:23 +0000 (UTC) Received: from fenglinw02.ap.qualcomm.com (unknown [180.166.53.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: fenglinw) by smtp.codeaurora.org (Postfix) with ESMTPSA id 3CF49C433F1; Tue, 27 Apr 2021 10:24:20 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 3CF49C433F1 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=fenglinw@codeaurora.org From: Fenglin Wu To: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Lee Jones , Rob Herring , Fenglin Wu , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org Cc: subbaram@codeaurora.org, collinsd@codeaurora.org, aghayal@codeaurora.org Subject: [PATCH 1/2] dt-bindings: pwm: add bindings for PWM modules inside QCOM PMICs Date: Tue, 27 Apr 2021 18:22:09 +0800 Message-Id: <20210427102247.822-2-fenglinw@codeaurora.org> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20210427102247.822-1-fenglinw@codeaurora.org> References: <20210427102247.822-1-fenglinw@codeaurora.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add bindings for QCOM PMIC PWM modules which are accessed through SPMI bus. Signed-off-by: Fenglin Wu --- .../devicetree/bindings/pwm/pwm-qcom.yaml | 51 ++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-qcom.yaml diff --git a/Documentation/devicetree/bindings/pwm/pwm-qcom.yaml b/Documentation/devicetree/bindings/pwm/pwm-qcom.yaml new file mode 100644 index 0000000..e8d8ed6 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-qcom.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/pwm-qcom.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. PMIC PWM bindings + +maintainers: + - Fenglin Wu + +description: + PWM modules inside Qualcomm Technologies, Inc. PMICs can be accessed through + SPMI bus and normally one PMIC would have multiple PWM modules with adjacent + SPMI address space. + +Properties: + compatible: + const: qcom,pwm + + reg: + description: + The SPMI address base of the PWM module, if there are multiple PWM + modules present with adjacent SPMI address space, only need to specify + the address base of the 1st PWM module. + + "#pwm-cells": + # See pwm.yaml in this directory for a description of the cells format. + const: 2 + + qcom,num-channels: + description: + The number of the PWM channels (modules) with the adjacent SPMI address + space following the address base in "reg" property. + +required: + - compatible + - reg + - "#pwm-cells" + - qcom,num-channels + +additionalProperties: false + +examples: + - | + pm8350c_pwm: pwms@e800 { + compatible = "qcom,pwm"; + reg = <0xe800>; + #pwm-cells = <2>; + qcom,num-channels = <4>; + };