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[66.131.184.68]) by smtp.gmail.com with ESMTPSA id h12sm3211228qkj.52.2021.05.13.12.56.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 May 2021 12:56:47 -0700 (PDT) From: Jonathan Marek To: linux-arm-msm@vger.kernel.org Cc: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 1/2] clk: qcom: add support for SM8350 DISPCC Date: Thu, 13 May 2021 15:56:16 -0400 Message-Id: <20210513195617.15068-1-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support to the SM8350 display clock controller by extending the SM8250 display clock controller, which is almost identical but has some minor differences. Signed-off-by: Jonathan Marek --- drivers/clk/qcom/Kconfig | 4 +- drivers/clk/qcom/dispcc-sm8250.c | 84 +++++++++++++++++++++++++++----- 2 files changed, 75 insertions(+), 13 deletions(-) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 45646b867cdb..cc60e6ee1654 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -484,11 +484,11 @@ config SDX_GCC_55 SPI, I2C, USB, SD/UFS, PCIe etc. config SM_DISPCC_8250 - tristate "SM8150 and SM8250 Display Clock Controller" + tristate "SM8150/SM8250/SM8350 Display Clock Controller" depends on SM_GCC_8150 || SM_GCC_8250 help Support for the display clock controller on Qualcomm Technologies, Inc - SM8150 and SM8250 devices. + SM8150/SM8250/SM8350 devices. Say Y if you want to support display devices and functionality such as splash screen. diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c index de09cd5c209f..1fcf8085a109 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -36,6 +36,10 @@ static struct pll_vco vco_table[] = { { 249600000, 2000000000, 0 }, }; +static struct pll_vco lucid_5lpe_vco[] = { + { 249600000, 1750000000, 0 }, +}; + static struct alpha_pll_config disp_cc_pll0_config = { .l = 0x47, .alpha = 0xE000, @@ -1039,6 +1043,7 @@ static const struct qcom_cc_desc disp_cc_sm8250_desc = { static const struct of_device_id disp_cc_sm8250_match_table[] = { { .compatible = "qcom,sm8150-dispcc" }, { .compatible = "qcom,sm8250-dispcc" }, + { .compatible = "qcom,sm8350-dispcc" }, { } }; MODULE_DEVICE_TABLE(of, disp_cc_sm8250_match_table); @@ -1051,19 +1056,76 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); - /* note: trion == lucid, except for the prepare() op */ - BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID); - if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) { - disp_cc_pll0_config.config_ctl_hi_val = 0x00002267; - disp_cc_pll0_config.config_ctl_hi1_val = 0x00000024; - disp_cc_pll0_config.user_ctl_hi1_val = 0x000000D0; - disp_cc_pll0_init.ops = &clk_alpha_pll_trion_ops; - disp_cc_pll1_config.config_ctl_hi_val = 0x00002267; - disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024; - disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0; - disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops; + /* SM8350 has _SRC clocks offset by 4, and some other differences */ + if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8350-dispcc")) { + static struct clk_rcg2* const rcgs[] = { + &disp_cc_mdss_byte0_clk_src, + &disp_cc_mdss_byte1_clk_src, + &disp_cc_mdss_dp_aux1_clk_src, + &disp_cc_mdss_dp_aux_clk_src, + &disp_cc_mdss_dp_link1_clk_src, + &disp_cc_mdss_dp_link_clk_src, + &disp_cc_mdss_dp_pixel1_clk_src, + &disp_cc_mdss_dp_pixel2_clk_src, + &disp_cc_mdss_dp_pixel_clk_src, + &disp_cc_mdss_esc0_clk_src, + &disp_cc_mdss_mdp_clk_src, + &disp_cc_mdss_pclk0_clk_src, + &disp_cc_mdss_pclk1_clk_src, + &disp_cc_mdss_rot_clk_src, + &disp_cc_mdss_vsync_clk_src, + }; + static struct clk_regmap_div* const divs[] = { + &disp_cc_mdss_byte0_div_clk_src, + &disp_cc_mdss_byte1_div_clk_src, + &disp_cc_mdss_dp_link1_div_clk_src, + &disp_cc_mdss_dp_link_div_clk_src, + }; + unsigned i; + static bool offset_applied = false; + + /* only apply the offsets once (in case of deferred probe) */ + if (!offset_applied) { + for (i = 0; i < ARRAY_SIZE(rcgs); i++) + rcgs[i]->cmd_rcgr -= 4; + + for (i = 0; i < ARRAY_SIZE(divs); i++) { + divs[i]->reg -= 4; + divs[i]->width = 4; + } + + disp_cc_mdss_ahb_clk.halt_reg -= 4; + disp_cc_mdss_ahb_clk.clkr.enable_reg -= 4; + + offset_applied = true; + } + + disp_cc_mdss_ahb_clk_src.cmd_rcgr = 0x22a0; + + disp_cc_pll0_config.config_ctl_hi1_val = 0x2A9A699C; + disp_cc_pll0_config.test_ctl_hi1_val = 0x01800000; + disp_cc_pll0_init.ops = &clk_alpha_pll_lucid_5lpe_ops; + disp_cc_pll0.vco_table = lucid_5lpe_vco; + disp_cc_pll1_config.config_ctl_hi1_val = 0x2A9A699C; + disp_cc_pll1_config.test_ctl_hi1_val = 0x01800000; + disp_cc_pll1_init.ops = &clk_alpha_pll_lucid_5lpe_ops; + disp_cc_pll1.vco_table = lucid_5lpe_vco; + } else { + /* note: trion == lucid, except for the prepare() op */ + BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID); + if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) { + disp_cc_pll0_config.config_ctl_hi_val = 0x00002267; + disp_cc_pll0_config.config_ctl_hi1_val = 0x00000024; + disp_cc_pll0_config.user_ctl_hi1_val = 0x000000D0; + disp_cc_pll0_init.ops = &clk_alpha_pll_trion_ops; + disp_cc_pll1_config.config_ctl_hi_val = 0x00002267; + disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024; + disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0; + disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops; + } } + /* note for SM8350: downstream lucid_5lpe configure differs slightly */ clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); clk_lucid_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);