diff mbox series

[v3,3/4] drm/msm/dpu: use struct dpu_hw_merge_3d in dpu_hw_pingpong

Message ID 20210515190909.1809050-4-dmitry.baryshkov@linaro.org (mailing list archive)
State New
Headers show
Series drm/msm/dpu: simplify dpu_hw_blk handling | expand

Commit Message

Dmitry Baryshkov May 15, 2021, 7:09 p.m. UTC
Use struct dpu_hw_merge_3d pointer in struct dpu_hw_pingpong rather
than using struct dpu_hw_blk. This is the only user of dpu_hw_blk.id,
which will be cleaned in the next patch.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 11 ++++-------
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h      |  4 +++-
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c               |  2 +-
 3 files changed, 8 insertions(+), 9 deletions(-)

Comments

Abhinav Kumar June 4, 2021, 9:09 p.m. UTC | #1
On 2021-05-15 12:09, Dmitry Baryshkov wrote:
> Use struct dpu_hw_merge_3d pointer in struct dpu_hw_pingpong rather
> than using struct dpu_hw_blk. This is the only user of dpu_hw_blk.id,
> which will be cleaned in the next patch.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 11 ++++-------
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h      |  4 +++-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c               |  2 +-
>  3 files changed, 8 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> index 0e06b7e73c7a..4feec24162bc 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> @@ -284,7 +284,7 @@ static void 
> dpu_encoder_phys_vid_setup_timing_engine(
>  	intf_cfg.stream_sel = 0; /* Don't care value for video mode */
>  	intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
>  	if (phys_enc->hw_pp->merge_3d)
> -		intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->id;
> +		intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx;
> 
>  	spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
>  	phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf,
> @@ -298,11 +298,8 @@ static void 
> dpu_encoder_phys_vid_setup_timing_engine(
>  				true,
>  				phys_enc->hw_pp->idx);
> 
> -	if (phys_enc->hw_pp->merge_3d) {
> -		struct dpu_hw_merge_3d *merge_3d =
> to_dpu_hw_merge_3d(phys_enc->hw_pp->merge_3d);
> -
> -		merge_3d->ops.setup_3d_mode(merge_3d, intf_cfg.mode_3d);
> -	}
> +	if (phys_enc->hw_pp->merge_3d)
> +		phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d,
> intf_cfg.mode_3d);
> 
>  	spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
> 
> @@ -461,7 +458,7 @@ static void dpu_encoder_phys_vid_enable(struct
> dpu_encoder_phys *phys_enc)
> 
>  	ctl->ops.update_pending_flush_intf(ctl, phys_enc->hw_intf->idx);
>  	if (ctl->ops.update_pending_flush_merge_3d && 
> phys_enc->hw_pp->merge_3d)
> -		ctl->ops.update_pending_flush_merge_3d(ctl, 
> phys_enc->hw_pp->merge_3d->id);
> +		ctl->ops.update_pending_flush_merge_3d(ctl, 
> phys_enc->hw_pp->merge_3d->idx);
> 
>  skip_flush:
>  	DPU_DEBUG_VIDENC(phys_enc,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
> index 845b9ce80e31..89d08a715c16 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
> @@ -126,6 +126,8 @@ struct dpu_hw_pingpong_ops {
>  			struct dpu_hw_dither_cfg *cfg);
>  };
> 
> +struct dpu_hw_merge_3d;
> +
>  struct dpu_hw_pingpong {
>  	struct dpu_hw_blk base;
>  	struct dpu_hw_blk_reg_map hw;
> @@ -133,7 +135,7 @@ struct dpu_hw_pingpong {
>  	/* pingpong */
>  	enum dpu_pingpong idx;
>  	const struct dpu_pingpong_cfg *caps;
> -	struct dpu_hw_blk *merge_3d;
> +	struct dpu_hw_merge_3d *merge_3d;
> 
>  	/* ops */
>  	struct dpu_hw_pingpong_ops ops;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> index fd2d104f0a91..c0eec12498e7 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> @@ -162,7 +162,7 @@ int dpu_rm_init(struct dpu_rm *rm,
>  			goto fail;
>  		}
>  		if (pp->merge_3d && pp->merge_3d < MERGE_3D_MAX)
> -			hw->merge_3d = rm->merge_3d_blks[pp->merge_3d - MERGE_3D_0];
> +			hw->merge_3d = to_dpu_hw_merge_3d(rm->merge_3d_blks[pp->merge_3d -
> MERGE_3D_0]);
>  		rm->pingpong_blks[pp->id - PINGPONG_0] = &hw->base;
>  	}
diff mbox series

Patch

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 0e06b7e73c7a..4feec24162bc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -284,7 +284,7 @@  static void dpu_encoder_phys_vid_setup_timing_engine(
 	intf_cfg.stream_sel = 0; /* Don't care value for video mode */
 	intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
 	if (phys_enc->hw_pp->merge_3d)
-		intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->id;
+		intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx;
 
 	spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
 	phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf,
@@ -298,11 +298,8 @@  static void dpu_encoder_phys_vid_setup_timing_engine(
 				true,
 				phys_enc->hw_pp->idx);
 
-	if (phys_enc->hw_pp->merge_3d) {
-		struct dpu_hw_merge_3d *merge_3d = to_dpu_hw_merge_3d(phys_enc->hw_pp->merge_3d);
-
-		merge_3d->ops.setup_3d_mode(merge_3d, intf_cfg.mode_3d);
-	}
+	if (phys_enc->hw_pp->merge_3d)
+		phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d, intf_cfg.mode_3d);
 
 	spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
 
@@ -461,7 +458,7 @@  static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc)
 
 	ctl->ops.update_pending_flush_intf(ctl, phys_enc->hw_intf->idx);
 	if (ctl->ops.update_pending_flush_merge_3d && phys_enc->hw_pp->merge_3d)
-		ctl->ops.update_pending_flush_merge_3d(ctl, phys_enc->hw_pp->merge_3d->id);
+		ctl->ops.update_pending_flush_merge_3d(ctl, phys_enc->hw_pp->merge_3d->idx);
 
 skip_flush:
 	DPU_DEBUG_VIDENC(phys_enc,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
index 845b9ce80e31..89d08a715c16 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
@@ -126,6 +126,8 @@  struct dpu_hw_pingpong_ops {
 			struct dpu_hw_dither_cfg *cfg);
 };
 
+struct dpu_hw_merge_3d;
+
 struct dpu_hw_pingpong {
 	struct dpu_hw_blk base;
 	struct dpu_hw_blk_reg_map hw;
@@ -133,7 +135,7 @@  struct dpu_hw_pingpong {
 	/* pingpong */
 	enum dpu_pingpong idx;
 	const struct dpu_pingpong_cfg *caps;
-	struct dpu_hw_blk *merge_3d;
+	struct dpu_hw_merge_3d *merge_3d;
 
 	/* ops */
 	struct dpu_hw_pingpong_ops ops;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index fd2d104f0a91..c0eec12498e7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -162,7 +162,7 @@  int dpu_rm_init(struct dpu_rm *rm,
 			goto fail;
 		}
 		if (pp->merge_3d && pp->merge_3d < MERGE_3D_MAX)
-			hw->merge_3d = rm->merge_3d_blks[pp->merge_3d - MERGE_3D_0];
+			hw->merge_3d = to_dpu_hw_merge_3d(rm->merge_3d_blks[pp->merge_3d - MERGE_3D_0]);
 		rm->pingpong_blks[pp->id - PINGPONG_0] = &hw->base;
 	}