diff mbox series

[v2,2/3] arm64: dts: qcom: sm8250: Add SDHCI2 pinctrl

Message ID 20210612192358.62602-2-konrad.dybcio@somainline.org (mailing list archive)
State Superseded
Headers show
Series [v2,1/3] arm64: dts: qcom: sm8250: Disable Adreno and Venus by default | expand

Commit Message

Konrad Dybcio June 12, 2021, 7:23 p.m. UTC
Add required pins for SDHCI2, so that the interface can work reliably.
The configuration comes from a MTP board, which conveniently means it's
going to be correct for the vast majority of phones (and other devices).

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
Changes since v1:
- Separate this into its own patch

 arch/arm64/boot/dts/qcom/sm8250.dtsi | 32 ++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

Comments

Bjorn Andersson June 15, 2021, 11:39 p.m. UTC | #1
On Sat 12 Jun 14:23 CDT 2021, Konrad Dybcio wrote:

> Add required pins for SDHCI2, so that the interface can work reliably.
> The configuration comes from a MTP board, which conveniently means it's
> going to be correct for the vast majority of phones (and other devices).
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> ---
> Changes since v1:
> - Separate this into its own patch
> 
>  arch/arm64/boot/dts/qcom/sm8250.dtsi | 32 ++++++++++++++++++++++++++++
>  1 file changed, 32 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> index fc1049c2bb11..fe858abbff5d 100644
> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> @@ -8,6 +8,7 @@
>  #include <dt-bindings/clock/qcom,gcc-sm8250.h>
>  #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
>  #include <dt-bindings/clock/qcom,rpmh.h>
> +#include <dt-bindings/gpio/gpio.h>
>  #include <dt-bindings/interconnect/qcom,osm-l3.h>
>  #include <dt-bindings/interconnect/qcom,sm8250.h>
>  #include <dt-bindings/mailbox/qcom-ipcc.h>
> @@ -2157,6 +2158,10 @@ sdhc_2: sdhci@8804000 {
>  			power-domains = <&rpmhpd SM8250_CX>;
>  			operating-points-v2 = <&sdhc2_opp_table>;
>  
> +			cd-gpios = <&tlmm 77 GPIO_ACTIVE_HIGH>;
> +			pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>;
> +			pinctrl-names = "default";
> +
>  			status = "disabled";
>  
>  			sdhc2_opp_table: sdhc2-opp-table {
> @@ -3401,6 +3406,33 @@ ws {
>  					output-high;
>  				};
>  			};
> +
> +			sdc2_default_state: sdc2-default {
> +				clk {
> +					pins = "sdc2_clk";
> +					drive-strength = <16>;

The fact that RB5 has these as 16/10/10 seems to show that these should
be board-specific (as we typically have them). So please follow that.


(The sleep state on other hand is not going to change, so that I'm okay
with you define here for all boards to use).

Regards,
Bjorn

> +					bias-disable;
> +				};
> +
> +				cmd {
> +					pins = "sdc2_cmd";
> +					drive-strength = <16>;
> +					bias-pull-up;
> +				};
> +
> +				data {
> +					pins = "sdc2_data";
> +					drive-strength = <16>;
> +					bias-pull-up;
> +				};
> +			};
> +
> +			sdc2_card_det_n: sd-card-det-n {
> +				pins = "gpio77";
> +				function = "gpio";
> +				bias-pull-up;
> +				drive-strength = <2>;
> +			};
>  		};
>  
>  		apps_smmu: iommu@15000000 {
> -- 
> 2.32.0
>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index fc1049c2bb11..fe858abbff5d 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -8,6 +8,7 @@ 
 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interconnect/qcom,osm-l3.h>
 #include <dt-bindings/interconnect/qcom,sm8250.h>
 #include <dt-bindings/mailbox/qcom-ipcc.h>
@@ -2157,6 +2158,10 @@  sdhc_2: sdhci@8804000 {
 			power-domains = <&rpmhpd SM8250_CX>;
 			operating-points-v2 = <&sdhc2_opp_table>;
 
+			cd-gpios = <&tlmm 77 GPIO_ACTIVE_HIGH>;
+			pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>;
+			pinctrl-names = "default";
+
 			status = "disabled";
 
 			sdhc2_opp_table: sdhc2-opp-table {
@@ -3401,6 +3406,33 @@  ws {
 					output-high;
 				};
 			};
+
+			sdc2_default_state: sdc2-default {
+				clk {
+					pins = "sdc2_clk";
+					drive-strength = <16>;
+					bias-disable;
+				};
+
+				cmd {
+					pins = "sdc2_cmd";
+					drive-strength = <16>;
+					bias-pull-up;
+				};
+
+				data {
+					pins = "sdc2_data";
+					drive-strength = <16>;
+					bias-pull-up;
+				};
+			};
+
+			sdc2_card_det_n: sd-card-det-n {
+				pins = "gpio77";
+				function = "gpio";
+				bias-pull-up;
+				drive-strength = <2>;
+			};
 		};
 
 		apps_smmu: iommu@15000000 {