diff mbox series

[RFC,v1,05/11] dt-bindings: clock: Add QCOM SM8350 display clock bindings

Message ID 20210616141107.291430-6-robert.foss@linaro.org (mailing list archive)
State Not Applicable, archived
Headers show
Series Qcom SM8350 DispCC & VideoCC | expand

Commit Message

Robert Foss June 16, 2021, 2:11 p.m. UTC
Add device tree bindings for display clock controller for
Qualcomm Technology Inc's SM8350 SoC.

Signed-off-by: Robert Foss <robert.foss@linaro.org>
---
 .../bindings/clock/qcom,dispcc-sm8x50.yaml    |  6 +-
 .../dt-bindings/clock/qcom,dispcc-sm8350.h    | 77 +++++++++++++++++++
 2 files changed, 81 insertions(+), 2 deletions(-)
 create mode 100644 include/dt-bindings/clock/qcom,dispcc-sm8350.h

Comments

Rob Herring June 24, 2021, 9:18 p.m. UTC | #1
On Wed, Jun 16, 2021 at 04:11:01PM +0200, Robert Foss wrote:
> Add device tree bindings for display clock controller for
> Qualcomm Technology Inc's SM8350 SoC.
> 
> Signed-off-by: Robert Foss <robert.foss@linaro.org>
> ---
>  .../bindings/clock/qcom,dispcc-sm8x50.yaml    |  6 +-
>  .../dt-bindings/clock/qcom,dispcc-sm8350.h    | 77 +++++++++++++++++++
>  2 files changed, 81 insertions(+), 2 deletions(-)
>  create mode 100644 include/dt-bindings/clock/qcom,dispcc-sm8350.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
> index 0cdf53f41f84..c10eefd024f6 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
> @@ -4,24 +4,26 @@
>  $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
>  $schema: http://devicetree.org/meta-schemas/core.yaml#
>  
> -title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250
> +title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250/SM8350
>  
>  maintainers:
>    - Jonathan Marek <jonathan@marek.ca>
>  
>  description: |
>    Qualcomm display clock control module which supports the clocks, resets and
> -  power domains on SM8150 and SM8250.
> +  power domains on SM8150, SM8250 and SM8350.
>  
>    See also:
>      dt-bindings/clock/qcom,dispcc-sm8150.h
>      dt-bindings/clock/qcom,dispcc-sm8250.h
> +    dt-bindings/clock/qcom,dispcc-sm8350.h
>  
>  properties:
>    compatible:
>      enum:
>        - qcom,sm8150-dispcc
>        - qcom,sm8250-dispcc
> +      - qcom,sm8350-dispcc
>  
>    clocks:
>      items:
> diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8350.h b/include/dt-bindings/clock/qcom,dispcc-sm8350.h
> new file mode 100644
> index 000000000000..361ef27de585
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,dispcc-sm8350.h
> @@ -0,0 +1,77 @@
> +/* SPDX-License-Identifier: GPL-2.0 */

I'm tired of saying this for QCom bindings given it's been QCom I've 
gotten complaints on DT licensing, but dual license please. Spread the 
word.

I'm sure if someone audited licenses of headers and dts files they'd 
find a mess.

Rob
Robert Foss June 25, 2021, 1:51 p.m. UTC | #2
On Thu, 24 Jun 2021 at 23:18, Rob Herring <robh@kernel.org> wrote:
>
> On Wed, Jun 16, 2021 at 04:11:01PM +0200, Robert Foss wrote:
> > Add device tree bindings for display clock controller for
> > Qualcomm Technology Inc's SM8350 SoC.
> >
> > Signed-off-by: Robert Foss <robert.foss@linaro.org>
> > ---
> >  .../bindings/clock/qcom,dispcc-sm8x50.yaml    |  6 +-
> >  .../dt-bindings/clock/qcom,dispcc-sm8350.h    | 77 +++++++++++++++++++
> >  2 files changed, 81 insertions(+), 2 deletions(-)
> >  create mode 100644 include/dt-bindings/clock/qcom,dispcc-sm8350.h
> >
> > diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
> > index 0cdf53f41f84..c10eefd024f6 100644
> > --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
> > +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
> > @@ -4,24 +4,26 @@
> >  $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
> >  $schema: http://devicetree.org/meta-schemas/core.yaml#
> >
> > -title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250
> > +title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250/SM8350
> >
> >  maintainers:
> >    - Jonathan Marek <jonathan@marek.ca>
> >
> >  description: |
> >    Qualcomm display clock control module which supports the clocks, resets and
> > -  power domains on SM8150 and SM8250.
> > +  power domains on SM8150, SM8250 and SM8350.
> >
> >    See also:
> >      dt-bindings/clock/qcom,dispcc-sm8150.h
> >      dt-bindings/clock/qcom,dispcc-sm8250.h
> > +    dt-bindings/clock/qcom,dispcc-sm8350.h
> >
> >  properties:
> >    compatible:
> >      enum:
> >        - qcom,sm8150-dispcc
> >        - qcom,sm8250-dispcc
> > +      - qcom,sm8350-dispcc
> >
> >    clocks:
> >      items:
> > diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8350.h b/include/dt-bindings/clock/qcom,dispcc-sm8350.h
> > new file mode 100644
> > index 000000000000..361ef27de585
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/qcom,dispcc-sm8350.h
> > @@ -0,0 +1,77 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
>
> I'm tired of saying this for QCom bindings given it's been QCom I've
> gotten complaints on DT licensing, but dual license please. Spread the
> word.
>
> I'm sure if someone audited licenses of headers and dts files they'd
> find a mess.

Thanks for pointing this out. I'll keep an eye out and change it to
(GPL-2.0-only OR BSD-2-Clause).
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
index 0cdf53f41f84..c10eefd024f6 100644
--- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
@@ -4,24 +4,26 @@ 
 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250
+title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250/SM8350
 
 maintainers:
   - Jonathan Marek <jonathan@marek.ca>
 
 description: |
   Qualcomm display clock control module which supports the clocks, resets and
-  power domains on SM8150 and SM8250.
+  power domains on SM8150, SM8250 and SM8350.
 
   See also:
     dt-bindings/clock/qcom,dispcc-sm8150.h
     dt-bindings/clock/qcom,dispcc-sm8250.h
+    dt-bindings/clock/qcom,dispcc-sm8350.h
 
 properties:
   compatible:
     enum:
       - qcom,sm8150-dispcc
       - qcom,sm8250-dispcc
+      - qcom,sm8350-dispcc
 
   clocks:
     items:
diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8350.h b/include/dt-bindings/clock/qcom,dispcc-sm8350.h
new file mode 100644
index 000000000000..361ef27de585
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,dispcc-sm8350.h
@@ -0,0 +1,77 @@ 
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021, Linaro Limited
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8350_H
+#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8350_H
+
+/* DISP_CC clock registers */
+#define DISP_CC_MDSS_AHB_CLK			0
+#define DISP_CC_MDSS_AHB_CLK_SRC		1
+#define DISP_CC_MDSS_BYTE0_CLK			2
+#define DISP_CC_MDSS_BYTE0_CLK_SRC		3
+#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC		4
+#define DISP_CC_MDSS_BYTE0_INTF_CLK		5
+#define DISP_CC_MDSS_BYTE1_CLK			6
+#define DISP_CC_MDSS_BYTE1_CLK_SRC		7
+#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC		8
+#define DISP_CC_MDSS_BYTE1_INTF_CLK		9
+#define DISP_CC_MDSS_DP_AUX1_CLK		10
+#define DISP_CC_MDSS_DP_AUX1_CLK_SRC		11
+#define DISP_CC_MDSS_DP_AUX_CLK			12
+#define DISP_CC_MDSS_DP_AUX_CLK_SRC		13
+#define DISP_CC_MDSS_DP_LINK1_CLK		14
+#define DISP_CC_MDSS_DP_LINK1_CLK_SRC		15
+#define DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC	16
+#define DISP_CC_MDSS_DP_LINK1_INTF_CLK		17
+#define DISP_CC_MDSS_DP_LINK_CLK		18
+#define DISP_CC_MDSS_DP_LINK_CLK_SRC		19
+#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC	20
+#define DISP_CC_MDSS_DP_LINK_INTF_CLK		21
+#define DISP_CC_MDSS_DP_PIXEL1_CLK		22
+#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC		23
+#define DISP_CC_MDSS_DP_PIXEL2_CLK		24
+#define DISP_CC_MDSS_DP_PIXEL2_CLK_SRC		25
+#define DISP_CC_MDSS_DP_PIXEL_CLK		26
+#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC		27
+#define DISP_CC_MDSS_EDP_AUX_CLK		28
+#define DISP_CC_MDSS_EDP_AUX_CLK_SRC		29
+#define DISP_CC_MDSS_EDP_LINK_CLK		30
+#define DISP_CC_MDSS_EDP_LINK_CLK_SRC		31
+#define DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC	32
+#define DISP_CC_MDSS_EDP_LINK_INTF_CLK		33
+#define DISP_CC_MDSS_EDP_PIXEL_CLK		34
+#define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC		35
+#define DISP_CC_MDSS_ESC0_CLK			36
+#define DISP_CC_MDSS_ESC0_CLK_SRC		37
+#define DISP_CC_MDSS_ESC1_CLK			38
+#define DISP_CC_MDSS_ESC1_CLK_SRC		39
+#define DISP_CC_MDSS_MDP_CLK			40
+#define DISP_CC_MDSS_MDP_CLK_SRC		41
+#define DISP_CC_MDSS_MDP_LUT_CLK		42
+#define DISP_CC_MDSS_NON_GDSC_AHB_CLK		43
+#define DISP_CC_MDSS_PCLK0_CLK			44
+#define DISP_CC_MDSS_PCLK0_CLK_SRC		45
+#define DISP_CC_MDSS_PCLK1_CLK			46
+#define DISP_CC_MDSS_PCLK1_CLK_SRC		47
+#define DISP_CC_MDSS_ROT_CLK			48
+#define DISP_CC_MDSS_ROT_CLK_SRC		49
+#define DISP_CC_MDSS_RSCC_AHB_CLK		50
+#define DISP_CC_MDSS_RSCC_VSYNC_CLK		51
+#define DISP_CC_MDSS_VSYNC_CLK			52
+#define DISP_CC_MDSS_VSYNC_CLK_SRC		53
+#define DISP_CC_PLL0				54
+#define DISP_CC_PLL1				55
+#define DISP_CC_SLEEP_CLK			56
+#define DISP_CC_SLEEP_CLK_SRC			57
+#define DISP_CC_XO_CLK_SRC			58
+
+/* DISP_CC Reset */
+#define DISP_CC_MDSS_CORE_BCR			0
+#define DISP_CC_MDSS_RSCC_BCR			1
+
+/* DISP_CC GDSCR */
+#define MDSS_GDSC				0
+
+#endif