[v6,1/5] cpuidle: qcom_spm: Detach state machine from main SPM handling

Message ID	20210621181016.365009-2-angelogioacchino.delregno@somainline.org (mailing list archive)
State	Superseded
Headers	show Return-Path: <linux-arm-msm-owner@kernel.org> From: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> To: bjorn.andersson@linaro.org Cc: agross@kernel.org, daniel.lezcano@linaro.org, rjw@rjwysocki.net, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, phone-devel@vger.kernel.org, konrad.dybcio@somainline.org, marijn.suijten@somainline.org, martin.botka@somainline.org, jeffrey.l.hugo@gmail.com, jami.kettunen@somainline.org, ~postmarketos/upstreaming@lists.sr.ht, devicetree@vger.kernel.org, robh+dt@kernel.org, AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Subject: [PATCH v6 1/5] cpuidle: qcom_spm: Detach state machine from main SPM handling Date: Mon, 21 Jun 2021 20:10:12 +0200 Message-Id: <20210621181016.365009-2-angelogioacchino.delregno@somainline.org> In-Reply-To: <20210621181016.365009-1-angelogioacchino.delregno@somainline.org> References: <20210621181016.365009-1-angelogioacchino.delregno@somainline.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	Implement SPM/SAW for MSM8998 and SDM6xx \| expand [v6,0/5] Implement SPM/SAW for MSM8998 and SDM6xx [v6,1/5] cpuidle: qcom_spm: Detach state machine from main SPM handling [v6,2/5] dt-bindings: soc: qcom: Add devicetree binding for QCOM SPM [v6,3/5] soc: qcom: spm: Implement support for SAWv4.1, SDM630/660 L2 AVS [v6,4/5] soc: qcom: spm: Add compatible for MSM8998 SAWv4.1 L2 [v6,5/5] dt-bindings: soc: qcom: spm: Document SDM660 and MSM8998 compatibles

On Mon, Jun 21, 2021 at 08:10:12PM +0200, AngeloGioacchino Del Regno wrote: > In commit a871be6b8eee ("cpuidle: Convert Qualcomm SPM driver to a generic > CPUidle driver") the SPM driver has been converted to a > generic CPUidle driver: that was mainly made to simplify the > driver and that was a great accomplishment; > Though, it was ignored that the SPM driver is not used only > on the ARM architecture. > I don't really understand why you insist on writing that I deliberately "ignored" your use case when converting the driver. This is not true. Perhaps that's not actually what you meant but that's how it sounds to me. > In preparation for the enablement of SPM features on AArch64/ARM64, > split the cpuidle-qcom-spm driver in two: the CPUIdle related > state machine (currently used only on ARM SoCs) stays there, while > the SPM communication handling lands back in soc/qcom/spm.c and > also making sure to not discard the simplifications that were > introduced in the aforementioned commit. > > Since now the "two drivers" are split, the SCM dependency in the > main SPM handling is gone and for this reason it was also possible > to move the SPM initialization early: this will also make sure that > whenever the SAW CPUIdle driver is getting initialized, the SPM > driver will be ready to do the job. > > Please note that the anticipation of the SPM initialization was > also done to optimize the boot times on platforms that have their > CPU/L2 idle states managed by other means (such as PSCI), while > needing SAW initialization for other purposes, like AVS control. > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> > --- > drivers/cpuidle/Kconfig.arm | 1 + > drivers/cpuidle/cpuidle-qcom-spm.c | 324 +++++++---------------------- > drivers/soc/qcom/Kconfig | 9 + > drivers/soc/qcom/Makefile | 1 + > drivers/soc/qcom/spm.c | 198 ++++++++++++++++++ > include/soc/qcom/spm.h | 41 ++++ > 6 files changed, 325 insertions(+), 249 deletions(-) > create mode 100644 drivers/soc/qcom/spm.c > create mode 100644 include/soc/qcom/spm.h > > diff --git a/drivers/cpuidle/cpuidle-qcom-spm.c b/drivers/cpuidle/cpuidle-qcom-spm.c > index adf91a6e4d7d..091453135ea6 100644 > --- a/drivers/cpuidle/cpuidle-qcom-spm.c > +++ b/drivers/cpuidle/cpuidle-qcom-spm.c > [...] > +static int spm_cpuidle_register(int cpu) > { > + struct platform_device *pdev = NULL; > + struct device_node *cpu_node, *saw_node; > + struct cpuidle_qcom_spm_data data = { > + .cpuidle_driver = { > + .name = "qcom_spm", > + .owner = THIS_MODULE, > + .cpumask = (struct cpumask *)cpumask_of(cpu), > + .states[0] = { > + .enter = spm_enter_idle_state, > + .exit_latency = 1, > + .target_residency = 1, > + .power_usage = UINT_MAX, > + .name = "WFI", > + .desc = "ARM WFI", > + } > + } > + }; The stack is gone after the function returns. Stephan [ 0.756176] 8<--- cut here --- [ 0.756222] ledtrig-cpu: registered to indicate activity on CPUs [ 0.756566] 8<--- cut here --- [ 0.756567] 8<--- cut here --- [ 0.756570] Unable to handle kernel NULL pointer dereference at virtual address 00000000 [ 0.756571] Unable to handle kernel NULL pointer dereference at virtual address 00000000 [ 0.756577] pgd = (ptrval) [ 0.756578] pgd = (ptrval) [ 0.756583] [00000000] *pgd=00000000 [ 0.756583] [00000000] *pgd=00000000 [ 0.756588] [ 0.756597] Internal error: Oops: 80000005 [#1] PREEMPT SMP ARM [ 0.756605] Modules linked in: [ 0.756613] CPU: 3 PID: 0 Comm: swapper/3 Not tainted 5.13.0-rc7 #9 [ 0.756622] Hardware name: Generic DT based system [ 0.756626] PC is at 0x0 [ 0.756634] LR is at cpuidle_enter_state+0x12c/0x358 [ 0.756650] pc : [<00000000>] lr : [<c0609c6c>] psr: 60000093 [ 0.756656] sp : c1085f68 ip : 017dc905 fp : 00000000 [ 0.756662] r10: 00000000 r9 : c1059b28 r8 : ef000a30 [ 0.756668] r7 : c1059938 r6 : 2d183b16 r5 : c1059b18 r4 : 00000005 [ 0.756675] r3 : 00000000 r2 : 00000005 r1 : c1059938 r0 : ef000a30 [ 0.756682] Flags: nZCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment none [ 0.756691] Control: 10c5383d Table: 8000406a DAC: 00000051 [ 0.756696] Register r0 information: non-slab/vmalloc memory [ 0.756705] Register r1 information: non-slab/vmalloc memory [ 0.756713] Register r2 information: non-paged memory [ 0.756719] Register r3 information: NULL pointer [ 0.756726] Register r4 information: non-paged memory [ 0.756732] Register r5 information: non-slab/vmalloc memory [ 0.756739] Register r6 information: non-paged memory [ 0.756746] Register r7 information: non-slab/vmalloc memory [ 0.756753] Register r8 information: non-slab/vmalloc memory [ 0.756760] Register r9 information: non-slab/vmalloc memory [ 0.756767] Register r10 information: NULL pointer [ 0.756773] Register r11 information: NULL pointer [ 0.756780] Register r12 information: non-paged memory [ 0.756787] Process swapper/3 (pid: 0, stack limit = 0x(ptrval)) [ 0.756794] Stack: (0xc1085f68 to 0xc1086000) [ 0.756804] 5f60: 00000000 c1084000 c1085fc3 ef000a30 c1059938 00000005 [ 0.756815] 5f80: c0c06090 2719c400 00000000 c1084000 c1059938 c0609edc 00000003 c1084000 [ 0.756826] 5fa0: c0c0604c ef000a30 c0b4ea28 c015d0f8 c1085fb0 00000005 00000093 c0cb2cc2 [ 0.756837] 5fc0: 00000051 b02e84c1 c1085ff8 00000093 00000051 10c0387d c1085ff8 8000406a [ 0.756848] 5fe0: 410fd030 00000000 00000000 c015d51c 8107806a 801015d0 00000000 00000000 [ 0.756861] [<c0609c6c>] (cpuidle_enter_state) from [<c0609edc>] (cpuidle_enter+0x30/0x40) [ 0.756883] [<c0609edc>] (cpuidle_enter) from [<c015d0f8>] (do_idle+0x210/0x2e8) [ 0.756904] [<c015d0f8>] (do_idle) from [<c015d51c>] (cpu_startup_entry+0x18/0x1c) [ 0.756920] [<c015d51c>] (cpu_startup_entry) from [<801015d0>] (0x801015d0) [ 0.756937] Code: bad PC value [ 0.756950] Internal error: Oops: 80000005 [#2] PREEMPT SMP ARM [ 0.756952] ---[ end trace 9857663ab4add8af ]--- [ 0.756957] Modules linked in: [ 0.756958] Kernel panic - not syncing: Attempted to kill the idle task! [ 0.756960] [ 0.756963] CPU: 1 PID: 0 Comm: swapper/1 Tainted: G D 5.13.0-rc7 #9 [ 0.756972] Hardware name: Generic DT based system [ 0.756976] PC is at 0x0 [ 0.756982] LR is at cpuidle_enter_state+0x12c/0x358 [ 0.756993] pc : [<00000000>] lr : [<c0609c6c>] psr: 60000093 [ 0.756999] sp : c1081f68 ip : 017dc905 fp : 00000000 [ 0.757005] r10: 00000000 r9 : c1059b28 r8 : eefe0a30 [ 0.757011] r7 : c1059938 r6 : 2d1844da r5 : c1059b18 r4 : 00000005 [ 0.757018] r3 : 00000000 r2 : 00000005 r1 : c1059938 r0 : eefe0a30 [ 0.757025] Flags: nZCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment none [ 0.757033] Control: 10c5383d Table: 8000406a DAC: 00000051 [ 0.757038] Register r0 information: non-slab/vmalloc memory [ 0.757047] Register r1 information: non-slab/vmalloc memory [ 0.757054] Register r2 information: non-paged memory [ 0.757061] Register r3 information: NULL pointer [ 0.757067] Register r4 information: non-paged memory [ 0.757074] Register r5 information: non-slab/vmalloc memory [ 0.757080] Register r6 information: non-paged memory [ 0.757087] Register r7 information: non-slab/vmalloc memory [ 0.757094] Register r8 information: non-slab/vmalloc memory [ 0.757101] Register r9 information: non-slab/vmalloc memory [ 0.757108] Register r10 information: NULL pointer [ 0.757114] Register r11 information: NULL pointer [ 0.757121] Register r12 information: non-paged memory [ 0.757128] Process swapper/1 (pid: 0, stack limit = 0x(ptrval)) [ 0.757134] Stack: (0xc1081f68 to 0xc1082000) [ 0.757144] 1f60: 00000000 c1080000 c1081fc3 eefe0a30 c1059938 00000005 [ 0.757155] 1f80: c0c06090 2719c400 00000000 c1080000 c1059938 c0609edc 00000001 c1080000 [ 0.757167] 1fa0: c0c0604c eefe0a30 c0b4ea28 c015d0f8 c1081fb0 00000005 00000093 c0cb2cc2 [ 0.757178] 1fc0: 00000051 cf41e4d1 c1081ff8 00000093 00000051 10c0387d c1081ff8 8000406a [ 0.757189] 1fe0: 410fd030 00000000 00000000 c015d51c 8107806a 801015d0 00000000 00000000 [ 0.757197] [<c0609c6c>] (cpuidle_enter_state) from [<c0609edc>] (cpuidle_enter+0x30/0x40) [ 0.757218] [<c0609edc>] (cpuidle_enter) from [<c015d0f8>] (do_idle+0x210/0x2e8) [ 0.757236] [<c015d0f8>] (do_idle) from [<c015d51c>] (cpu_startup_entry+0x18/0x1c) [ 0.757251] [<c015d51c>] (cpu_startup_entry) from [<801015d0>] (0x801015d0) [ 0.757267] Code: bad PC value [ 0.757271] ---[ end trace 9857663ab4add8b0 ]--- [ 0.761255] Unable to handle kernel NULL pointer dereference at virtual address 00000000 [ 0.761256] CPU2: stopping [ 0.761261] pgd = (ptrval) [ 0.761261] CPU: 2 PID: 1 Comm: swapper/0 Tainted: G D 5.13.0-rc7 #9 [ 0.761265] [00000000] *pgd=00000000 [ 0.761271] Hardware name: Generic DT based system [ 0.761275] Internal error: Oops: 80000005 [#3] PREEMPT SMP ARM [ 0.761281] Modules linked in: [ 0.761278] [<c010ee70>] (unwind_backtrace) from [<c010ac80>] (show_stack+0x10/0x14) [ 0.761287] CPU: 0 PID: 0 Comm: swapper/0 Tainted: G D 5.13.0-rc7 #9 [ 0.761296] Hardware name: Generic DT based system [ 0.761300] PC is at 0x0 [ 0.761299] [<c010ac80>] (show_stack) from [<c07bcbb0>] (dump_stack+0x94/0xa8) [ 0.761306] LR is at cpuidle_enter_state+0x12c/0x358 [ 0.761317] pc : [<00000000>] lr : [<c0609c6c>] psr: 60000093 [ 0.761323] sp : c0c01f28 ip : 017dc905 fp : 00000000 [ 0.761318] [<c07bcbb0>] (dump_stack) from [<c010ccbc>] (do_handle_IPI+0xf4/0x11c) [ 0.761329] r10: 00000000 r9 : c1059b28 r8 : eefd0a30 [ 0.761335] r7 : c1059938 r6 : 2d12399c r5 : c1059b18 r4 : 00000005 [ 0.761335] [<c010ccbc>] (do_handle_IPI) from [<c010ccfc>] (ipi_handler+0x18/0x20) [ 0.761341] r3 : 00000000 r2 : 00000005 r1 : c1059938 r0 : eefd0a30 [ 0.761348] Flags: nZCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment none [ 0.761356] Control: 10c5383d Table: 8000406a DAC: 00000051 [ 0.761350] [<c010ccfc>] (ipi_handler) from [<c018c898>] (handle_percpu_devid_irq+0x78/0x150) [ 0.761360] Register r0 information: non-slab/vmalloc memory [ 0.761369] Register r1 information: non-slab/vmalloc memory [ 0.761376] Register r2 information: [ 0.761368] [<c018c898>] (handle_percpu_devid_irq) from [<c01865d8>] (__handle_domain_irq+0x7c/0xd0) [ 0.761379] non-paged memory [ 0.761382] Register r3 information: NULL pointer [ 0.761389] Register r4 information: non-paged memory [ 0.761395] Register r5 information: [ 0.761389] [<c01865d8>] (__handle_domain_irq) from [<c04879f4>] (gic_handle_irq+0x70/0x84) [ 0.761398] non-slab/vmalloc memory [ 0.761402] Register r6 information: non-paged memory [ 0.761408] Register r7 information: non-slab/vmalloc memory [ 0.761415] Register r8 information: [ 0.761411] [<c04879f4>] (gic_handle_irq) from [<c0100b4c>] (__irq_svc+0x6c/0xa8) [ 0.761419] non-slab/vmalloc memory [ 0.761422] Register r9 information: non-slab/vmalloc memory [ 0.761427] Exception stack(0xc1059e28 to 0xc1059e70) [ 0.761429] Register r10 information: NULL pointer [ 0.761435] Register r11 information: [ 0.761437] 9e20: 60000093 2e4a2000 00000000 c0b48458 c0c060a8 00000034 [ 0.761440] NULL pointer [ 0.761443] Register r12 information: non-paged memory [ 0.761448] 9e40: c0cc8628 c1058000 60000013 00000000 c09fb5bc c0a614d4 00000143 c1059e78 [ 0.761449] Process swapper/0 (pid: 0, stack limit = 0x(ptrval)) [ 0.761456] 9e60: c0183ccc c0183cd0 60000013 ffffffff [ 0.761456] Stack: (0xc0c01f28 to 0xc0c02000) [ 0.761466] 1f20: 00000000 c0c00000 c0c01f83 eefd0a30 c1059938 00000005 [ 0.761462] [<c0100b4c>] (__irq_svc) from [<c0183cd0>] (vprintk_emit+0x17c/0x1d4) [ 0.761477] 1f40: c0c06090 26dcbb00 00000000 c0c00000 c1059938 c0609edc 00000000 c0c00000 [ 0.761479] [<c0183cd0>] (vprintk_emit) from [<c0183d4c>] (vprintk_default+0x24/0x2c) [ 0.761488] 1f60: c0c0604c eefd0a30 c0b4ea28 c015d0f8 c0c01f70 00000005 ef00cbc0 c0cb2cc2 [ 0.761498] 1f80: 00c00000 11feb622 c0b39a54 000000e1 c0c00000 00000001 c0b39a54 00000000 [ 0.761497] [<c0183d4c>] (vprintk_default) from [<c07ba87c>] (printk+0x30/0x54) [ 0.761509] 1fa0: ef00cbc0 c0b39a54 00000000 c015d51c c0cc6040 c0b00e34 ffffffff ffffffff [ 0.761520] 1fc0: 00000000 c0b00590 00000000 c0b39a54 11fbbb22 00000000 c0b00330 00000051 [ 0.761514] [<c07ba87c>] (printk) from [<c0b264a0>] (ledtrig_cpu_init+0xf0/0xfc) [ 0.761530] 1fe0: 10c0387d 00000000 81e00000 410fd030 10c5387d 00000000 00000000 00000000 [ 0.761534] [<c0b264a0>] (ledtrig_cpu_init) from [<c01017a4>] (do_one_initcall+0x50/0x1c4) [ 0.761537] [<c0609c6c>] (cpuidle_enter_state) from [<c0609edc>] (cpuidle_enter+0x30/0x40) [ 0.761552] [<c01017a4>] (do_one_initcall) from [<c0b010e0>] (kernel_init_freeable+0x22c/0x290) [ 0.761558] [<c0609edc>] (cpuidle_enter) from [<c015d0f8>] (do_idle+0x210/0x2e8) [ 0.761569] [<c0b010e0>] (kernel_init_freeable) from [<c07c014c>] (kernel_init+0x8/0x118) [ 0.761575] [<c015d0f8>] (do_idle) from [<c015d51c>] (cpu_startup_entry+0x18/0x1c) [ 0.761588] [<c07c014c>] (kernel_init) from [<c0100150>] (ret_from_fork+0x14/0x24) [ 0.761591] [<c015d51c>] (cpu_startup_entry) from [<c0b00e34>] (start_kernel+0x4e4/0x510) [ 0.761605] Exception stack(0xc1059fb0 to 0xc1059ff8) [ 0.761606] [<c0b00e34>] (start_kernel) from [<00000000>] (0x0) [ 0.761613] 9fa0: 00000000 00000000 00000000 00000000 [ 0.761620] Code: bad PC value [ 0.761623] 9fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 [ 0.761625] ---[ end trace 9857663ab4add8b1 ]--- [ 0.761632] 9fe0: 00000000 00000000 00000000 00000000 00000013 00000000 [ 1.740778] ---[ end Kernel panic - not syncing: Attempted to kill the idle task! ]---

diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm index 334f83e56120..8a02213c8391 100644 --- a/drivers/cpuidle/Kconfig.arm +++ b/drivers/cpuidle/Kconfig.arm @@ -112,6 +112,7 @@ config ARM_QCOM_SPM_CPUIDLE select CPU_IDLE_MULTIPLE_DRIVERS select DT_IDLE_STATES select QCOM_SCM + select QCOM_SPM help Select this to enable cpuidle for Qualcomm processors. The Subsystem Power Manager (SPM) controls low power modes for the diff --git a/drivers/cpuidle/cpuidle-qcom-spm.c b/drivers/cpuidle/cpuidle-qcom-spm.c index adf91a6e4d7d..091453135ea6 100644 --- a/drivers/cpuidle/cpuidle-qcom-spm.c +++ b/drivers/cpuidle/cpuidle-qcom-spm.c @@ -18,146 +18,18 @@ #include <linux/cpuidle.h> #include <linux/cpu_pm.h> #include <linux/qcom_scm.h> +#include <soc/qcom/spm.h> #include <asm/proc-fns.h> #include <asm/suspend.h> #include "dt_idle_states.h" -#define MAX_PMIC_DATA 2 -#define MAX_SEQ_DATA 64 -#define SPM_CTL_INDEX 0x7f -#define SPM_CTL_INDEX_SHIFT 4 -#define SPM_CTL_EN BIT(0) - -enum pm_sleep_mode { - PM_SLEEP_MODE_STBY, - PM_SLEEP_MODE_RET, - PM_SLEEP_MODE_SPC, - PM_SLEEP_MODE_PC, - PM_SLEEP_MODE_NR, -}; - -enum spm_reg { - SPM_REG_CFG, - SPM_REG_SPM_CTL, - SPM_REG_DLY, - SPM_REG_PMIC_DLY, - SPM_REG_PMIC_DATA_0, - SPM_REG_PMIC_DATA_1, - SPM_REG_VCTL, - SPM_REG_SEQ_ENTRY, - SPM_REG_SPM_STS, - SPM_REG_PMIC_STS, - SPM_REG_NR, -}; - -struct spm_reg_data { - const u8 *reg_offset; - u32 spm_cfg; - u32 spm_dly; - u32 pmic_dly; - u32 pmic_data[MAX_PMIC_DATA]; - u8 seq[MAX_SEQ_DATA]; - u8 start_index[PM_SLEEP_MODE_NR]; -}; - -struct spm_driver_data { +struct cpuidle_qcom_spm_data { struct cpuidle_driver cpuidle_driver; - void __iomem *reg_base; - const struct spm_reg_data *reg_data; -}; - -static const u8 spm_reg_offset_v2_1[SPM_REG_NR] = { - [SPM_REG_CFG] = 0x08, - [SPM_REG_SPM_CTL] = 0x30, - [SPM_REG_DLY] = 0x34, - [SPM_REG_SEQ_ENTRY] = 0x80, -}; - -/* SPM register data for 8974, 8084 */ -static const struct spm_reg_data spm_reg_8974_8084_cpu = { - .reg_offset = spm_reg_offset_v2_1, - .spm_cfg = 0x1, - .spm_dly = 0x3C102800, - .seq = { 0x03, 0x0B, 0x0F, 0x00, 0x20, 0x80, 0x10, 0xE8, 0x5B, 0x03, - 0x3B, 0xE8, 0x5B, 0x82, 0x10, 0x0B, 0x30, 0x06, 0x26, 0x30, - 0x0F }, - .start_index[PM_SLEEP_MODE_STBY] = 0, - .start_index[PM_SLEEP_MODE_SPC] = 3, + struct spm_driver_data *spm; }; -static const u8 spm_reg_offset_v1_1[SPM_REG_NR] = { - [SPM_REG_CFG] = 0x08, - [SPM_REG_SPM_CTL] = 0x20, - [SPM_REG_PMIC_DLY] = 0x24, - [SPM_REG_PMIC_DATA_0] = 0x28, - [SPM_REG_PMIC_DATA_1] = 0x2C, - [SPM_REG_SEQ_ENTRY] = 0x80, -}; - -/* SPM register data for 8064 */ -static const struct spm_reg_data spm_reg_8064_cpu = { - .reg_offset = spm_reg_offset_v1_1, - .spm_cfg = 0x1F, - .pmic_dly = 0x02020004, - .pmic_data[0] = 0x0084009C, - .pmic_data[1] = 0x00A4001C, - .seq = { 0x03, 0x0F, 0x00, 0x24, 0x54, 0x10, 0x09, 0x03, 0x01, - 0x10, 0x54, 0x30, 0x0C, 0x24, 0x30, 0x0F }, - .start_index[PM_SLEEP_MODE_STBY] = 0, - .start_index[PM_SLEEP_MODE_SPC] = 2, -}; - -static inline void spm_register_write(struct spm_driver_data *drv, - enum spm_reg reg, u32 val) -{ - if (drv->reg_data->reg_offset[reg]) - writel_relaxed(val, drv->reg_base + - drv->reg_data->reg_offset[reg]); -} - -/* Ensure a guaranteed write, before return */ -static inline void spm_register_write_sync(struct spm_driver_data *drv, - enum spm_reg reg, u32 val) -{ - u32 ret; - - if (!drv->reg_data->reg_offset[reg]) - return; - - do { - writel_relaxed(val, drv->reg_base + - drv->reg_data->reg_offset[reg]); - ret = readl_relaxed(drv->reg_base + - drv->reg_data->reg_offset[reg]); - if (ret == val) - break; - cpu_relax(); - } while (1); -} - -static inline u32 spm_register_read(struct spm_driver_data *drv, - enum spm_reg reg) -{ - return readl_relaxed(drv->reg_base + drv->reg_data->reg_offset[reg]); -} - -static void spm_set_low_power_mode(struct spm_driver_data *drv, - enum pm_sleep_mode mode) -{ - u32 start_index; - u32 ctl_val; - - start_index = drv->reg_data->start_index[mode]; - - ctl_val = spm_register_read(drv, SPM_REG_SPM_CTL); - ctl_val &= ~(SPM_CTL_INDEX << SPM_CTL_INDEX_SHIFT); - ctl_val |= start_index << SPM_CTL_INDEX_SHIFT; - ctl_val |= SPM_CTL_EN; - spm_register_write_sync(drv, SPM_REG_SPM_CTL, ctl_val); -} - static int qcom_pm_collapse(unsigned long int unused) { qcom_scm_cpu_power_down(QCOM_SCM_CPU_PWR_DOWN_L2_ON); @@ -189,156 +61,110 @@ static int qcom_cpu_spc(struct spm_driver_data *drv) static int spm_enter_idle_state(struct cpuidle_device *dev, struct cpuidle_driver *drv, int idx) { - struct spm_driver_data *data = container_of(drv, struct spm_driver_data, - cpuidle_driver); + struct cpuidle_qcom_spm_data *data = container_of(drv, struct cpuidle_qcom_spm_data, + cpuidle_driver); - return CPU_PM_CPU_IDLE_ENTER_PARAM(qcom_cpu_spc, idx, data); + return CPU_PM_CPU_IDLE_ENTER_PARAM(qcom_cpu_spc, idx, data->spm); } -static struct cpuidle_driver qcom_spm_idle_driver = { - .name = "qcom_spm", - .owner = THIS_MODULE, - .states[0] = { - .enter = spm_enter_idle_state, - .exit_latency = 1, - .target_residency = 1, - .power_usage = UINT_MAX, - .name = "WFI", - .desc = "ARM WFI", - } -}; - static const struct of_device_id qcom_idle_state_match[] = { { .compatible = "qcom,idle-state-spc", .data = spm_enter_idle_state }, { }, }; -static int spm_cpuidle_init(struct cpuidle_driver *drv, int cpu) +static int spm_cpuidle_register(int cpu) { + struct platform_device *pdev = NULL; + struct device_node *cpu_node, *saw_node; + struct cpuidle_qcom_spm_data data = { + .cpuidle_driver = { + .name = "qcom_spm", + .owner = THIS_MODULE, + .cpumask = (struct cpumask *)cpumask_of(cpu), + .states[0] = { + .enter = spm_enter_idle_state, + .exit_latency = 1, + .target_residency = 1, + .power_usage = UINT_MAX, + .name = "WFI", + .desc = "ARM WFI", + } + } + }; int ret; - memcpy(drv, &qcom_spm_idle_driver, sizeof(*drv)); - drv->cpumask = (struct cpumask *)cpumask_of(cpu); + cpu_node = of_cpu_device_node_get(cpu); + if (!cpu_node) + return -ENODEV; - /* Parse idle states from device tree */ - ret = dt_init_idle_driver(drv, qcom_idle_state_match, 1); - if (ret <= 0) - return ret ? : -ENODEV; + saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0); + if (!saw_node) + return -ENODEV; - /* We have atleast one power down mode */ - return qcom_scm_set_warm_boot_addr(cpu_resume_arm, drv->cpumask); -} + pdev = of_find_device_by_node(saw_node); + of_node_put(saw_node); + of_node_put(cpu_node); + if (!pdev) + return -ENODEV; -static struct spm_driver_data *spm_get_drv(struct platform_device *pdev, - int *spm_cpu) -{ - struct spm_driver_data *drv = NULL; - struct device_node *cpu_node, *saw_node; - int cpu; - bool found = 0; + data.spm = dev_get_drvdata(&pdev->dev); + if (!data.spm) + return -EINVAL; - for_each_possible_cpu(cpu) { - cpu_node = of_cpu_device_node_get(cpu); - if (!cpu_node) - continue; - saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0); - found = (saw_node == pdev->dev.of_node); - of_node_put(saw_node); - of_node_put(cpu_node); - if (found) - break; - } + ret = dt_init_idle_driver(&data.cpuidle_driver, + qcom_idle_state_match, 1); + if (ret <= 0) + return ret ? : -ENODEV; - if (found) { - drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL); - if (drv) - *spm_cpu = cpu; - } + ret = qcom_scm_set_warm_boot_addr(cpu_resume_arm, cpumask_of(cpu)); + if (ret) + return ret; - return drv; + return cpuidle_register(&data.cpuidle_driver, NULL); } -static const struct of_device_id spm_match_table[] = { - { .compatible = "qcom,msm8974-saw2-v2.1-cpu", - .data = &spm_reg_8974_8084_cpu }, - { .compatible = "qcom,apq8084-saw2-v2.1-cpu", - .data = &spm_reg_8974_8084_cpu }, - { .compatible = "qcom,apq8064-saw2-v1.1-cpu", - .data = &spm_reg_8064_cpu }, - { }, -}; - -static int spm_dev_probe(struct platform_device *pdev) +static int spm_cpuidle_drv_probe(struct platform_device *pdev) { - struct spm_driver_data *drv; - struct resource *res; - const struct of_device_id *match_id; - void __iomem *addr; int cpu, ret; if (!qcom_scm_is_available()) return -EPROBE_DEFER; - drv = spm_get_drv(pdev, &cpu); - if (!drv) - return -EINVAL; - platform_set_drvdata(pdev, drv); + for_each_possible_cpu(cpu) { + ret = spm_cpuidle_register(cpu); + if (ret && ret != -ENODEV) { + dev_err(&pdev->dev, + "Cannot register for CPU%d: %d\n", cpu, ret); + break; + } + } - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - drv->reg_base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(drv->reg_base)) - return PTR_ERR(drv->reg_base); + return ret; +} - match_id = of_match_node(spm_match_table, pdev->dev.of_node); - if (!match_id) - return -ENODEV; +static struct platform_driver spm_cpuidle_driver = { + .probe = spm_cpuidle_drv_probe, + .driver = { + .name = "qcom-spm-cpuidle", + }, +}; - drv->reg_data = match_id->data; +static int __init qcom_spm_cpuidle_init(void) +{ + struct platform_device *pdev; + int ret; - ret = spm_cpuidle_init(&drv->cpuidle_driver, cpu); + ret = platform_driver_register(&spm_cpuidle_driver); if (ret) return ret; - /* Write the SPM sequences first.. */ - addr = drv->reg_base + drv->reg_data->reg_offset[SPM_REG_SEQ_ENTRY]; - __iowrite32_copy(addr, drv->reg_data->seq, - ARRAY_SIZE(drv->reg_data->seq) / 4); - - /* - * ..and then the control registers. - * On some SoC if the control registers are written first and if the - * CPU was held in reset, the reset signal could trigger the SPM state - * machine, before the sequences are completely written. - */ - spm_register_write(drv, SPM_REG_CFG, drv->reg_data->spm_cfg); - spm_register_write(drv, SPM_REG_DLY, drv->reg_data->spm_dly); - spm_register_write(drv, SPM_REG_PMIC_DLY, drv->reg_data->pmic_dly); - spm_register_write(drv, SPM_REG_PMIC_DATA_0, - drv->reg_data->pmic_data[0]); - spm_register_write(drv, SPM_REG_PMIC_DATA_1, - drv->reg_data->pmic_data[1]); - - /* Set up Standby as the default low power mode */ - spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY); - - return cpuidle_register(&drv->cpuidle_driver, NULL); -} - -static int spm_dev_remove(struct platform_device *pdev) -{ - struct spm_driver_data *drv = platform_get_drvdata(pdev); + pdev = platform_device_register_simple("qcom-spm-cpuidle", + -1, NULL, 0); + if (IS_ERR(pdev)) { + platform_driver_unregister(&spm_cpuidle_driver); + return PTR_ERR(pdev); + } - cpuidle_unregister(&drv->cpuidle_driver); return 0; } - -static struct platform_driver spm_driver = { - .probe = spm_dev_probe, - .remove = spm_dev_remove, - .driver = { - .name = "saw", - .of_match_table = spm_match_table, - }, -}; - -builtin_platform_driver(spm_driver); +device_initcall(qcom_spm_cpuidle_init); diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index ac520e5eeefa..10b365f0bb8f 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -207,6 +207,15 @@ config QCOM_SOCINFO Say yes here to support the Qualcomm socinfo driver, providing information about the SoC to user space. +config QCOM_SPM + tristate "Qualcomm Subsystem Power Manager (SPM)" + depends on ARCH_QCOM + select QCOM_SCM + help + Enable the support for the Qualcomm Subsystem Power Manager, used + to manage cores, L2 low power modes and to configure the internal + Adaptive Voltage Scaler parameters, where supported. + config QCOM_WCNSS_CTRL tristate "Qualcomm WCNSS control driver" depends on ARCH_QCOM || COMPILE_TEST diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index 87a165c0ea10..0500283c2dc5 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_QCOM_SMEM_STATE) += smem_state.o obj-$(CONFIG_QCOM_SMP2P) += smp2p.o obj-$(CONFIG_QCOM_SMSM) += smsm.o obj-$(CONFIG_QCOM_SOCINFO) += socinfo.o +obj-$(CONFIG_QCOM_SPM) += spm.o obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o obj-$(CONFIG_QCOM_APR) += apr.o obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c new file mode 100644 index 000000000000..9b6f649c9a10 --- /dev/null +++ b/drivers/soc/qcom/spm.c @@ -0,0 +1,198 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2011-2014, The Linux Foundation. All rights reserved. + * Copyright (c) 2014,2015, Linaro Ltd. + * + * SAW power controller driver + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/slab.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/err.h> +#include <linux/platform_device.h> +#include <soc/qcom/spm.h> + +#define SPM_CTL_INDEX 0x7f +#define SPM_CTL_INDEX_SHIFT 4 +#define SPM_CTL_EN BIT(0) + +enum spm_reg { + SPM_REG_CFG, + SPM_REG_SPM_CTL, + SPM_REG_DLY, + SPM_REG_PMIC_DLY, + SPM_REG_PMIC_DATA_0, + SPM_REG_PMIC_DATA_1, + SPM_REG_VCTL, + SPM_REG_SEQ_ENTRY, + SPM_REG_SPM_STS, + SPM_REG_PMIC_STS, + SPM_REG_NR, +}; + +static const u8 spm_reg_offset_v2_1[SPM_REG_NR] = { + [SPM_REG_CFG] = 0x08, + [SPM_REG_SPM_CTL] = 0x30, + [SPM_REG_DLY] = 0x34, + [SPM_REG_SEQ_ENTRY] = 0x80, +}; + +/* SPM register data for 8974, 8084 */ +static const struct spm_reg_data spm_reg_8974_8084_cpu = { + .reg_offset = spm_reg_offset_v2_1, + .spm_cfg = 0x1, + .spm_dly = 0x3C102800, + .seq = { 0x03, 0x0B, 0x0F, 0x00, 0x20, 0x80, 0x10, 0xE8, 0x5B, 0x03, + 0x3B, 0xE8, 0x5B, 0x82, 0x10, 0x0B, 0x30, 0x06, 0x26, 0x30, + 0x0F }, + .start_index[PM_SLEEP_MODE_STBY] = 0, + .start_index[PM_SLEEP_MODE_SPC] = 3, +}; + +static const u8 spm_reg_offset_v1_1[SPM_REG_NR] = { + [SPM_REG_CFG] = 0x08, + [SPM_REG_SPM_CTL] = 0x20, + [SPM_REG_PMIC_DLY] = 0x24, + [SPM_REG_PMIC_DATA_0] = 0x28, + [SPM_REG_PMIC_DATA_1] = 0x2C, + [SPM_REG_SEQ_ENTRY] = 0x80, +}; + +/* SPM register data for 8064 */ +static const struct spm_reg_data spm_reg_8064_cpu = { + .reg_offset = spm_reg_offset_v1_1, + .spm_cfg = 0x1F, + .pmic_dly = 0x02020004, + .pmic_data[0] = 0x0084009C, + .pmic_data[1] = 0x00A4001C, + .seq = { 0x03, 0x0F, 0x00, 0x24, 0x54, 0x10, 0x09, 0x03, 0x01, + 0x10, 0x54, 0x30, 0x0C, 0x24, 0x30, 0x0F }, + .start_index[PM_SLEEP_MODE_STBY] = 0, + .start_index[PM_SLEEP_MODE_SPC] = 2, +}; + +static inline void spm_register_write(struct spm_driver_data *drv, + enum spm_reg reg, u32 val) +{ + if (drv->reg_data->reg_offset[reg]) + writel_relaxed(val, drv->reg_base + + drv->reg_data->reg_offset[reg]); +} + +/* Ensure a guaranteed write, before return */ +static inline void spm_register_write_sync(struct spm_driver_data *drv, + enum spm_reg reg, u32 val) +{ + u32 ret; + + if (!drv->reg_data->reg_offset[reg]) + return; + + do { + writel_relaxed(val, drv->reg_base + + drv->reg_data->reg_offset[reg]); + ret = readl_relaxed(drv->reg_base + + drv->reg_data->reg_offset[reg]); + if (ret == val) + break; + cpu_relax(); + } while (1); +} + +static inline u32 spm_register_read(struct spm_driver_data *drv, + enum spm_reg reg) +{ + return readl_relaxed(drv->reg_base + drv->reg_data->reg_offset[reg]); +} + +void spm_set_low_power_mode(struct spm_driver_data *drv, + enum pm_sleep_mode mode) +{ + u32 start_index; + u32 ctl_val; + + start_index = drv->reg_data->start_index[mode]; + + ctl_val = spm_register_read(drv, SPM_REG_SPM_CTL); + ctl_val &= ~(SPM_CTL_INDEX << SPM_CTL_INDEX_SHIFT); + ctl_val |= start_index << SPM_CTL_INDEX_SHIFT; + ctl_val |= SPM_CTL_EN; + spm_register_write_sync(drv, SPM_REG_SPM_CTL, ctl_val); +} + +static const struct of_device_id spm_match_table[] = { + { .compatible = "qcom,msm8974-saw2-v2.1-cpu", + .data = &spm_reg_8974_8084_cpu }, + { .compatible = "qcom,apq8084-saw2-v2.1-cpu", + .data = &spm_reg_8974_8084_cpu }, + { .compatible = "qcom,apq8064-saw2-v1.1-cpu", + .data = &spm_reg_8064_cpu }, + { }, +}; + +static int spm_dev_probe(struct platform_device *pdev) +{ + const struct of_device_id *match_id; + struct spm_driver_data *drv; + struct resource *res; + void __iomem *addr; + + drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL); + if (!drv) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + drv->reg_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(drv->reg_base)) + return PTR_ERR(drv->reg_base); + + match_id = of_match_node(spm_match_table, pdev->dev.of_node); + if (!match_id) + return -ENODEV; + + drv->reg_data = match_id->data; + platform_set_drvdata(pdev, drv); + + /* Write the SPM sequences first.. */ + addr = drv->reg_base + drv->reg_data->reg_offset[SPM_REG_SEQ_ENTRY]; + __iowrite32_copy(addr, drv->reg_data->seq, + ARRAY_SIZE(drv->reg_data->seq) / 4); + + /* + * ..and then the control registers. + * On some SoC if the control registers are written first and if the + * CPU was held in reset, the reset signal could trigger the SPM state + * machine, before the sequences are completely written. + */ + spm_register_write(drv, SPM_REG_CFG, drv->reg_data->spm_cfg); + spm_register_write(drv, SPM_REG_DLY, drv->reg_data->spm_dly); + spm_register_write(drv, SPM_REG_PMIC_DLY, drv->reg_data->pmic_dly); + spm_register_write(drv, SPM_REG_PMIC_DATA_0, + drv->reg_data->pmic_data[0]); + spm_register_write(drv, SPM_REG_PMIC_DATA_1, + drv->reg_data->pmic_data[1]); + + /* Set up Standby as the default low power mode */ + spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY); + + return 0; +} + +static struct platform_driver spm_driver = { + .probe = spm_dev_probe, + .driver = { + .name = "qcom_spm", + .of_match_table = spm_match_table, + }, +}; + +static int __init qcom_spm_init(void) +{ + return platform_driver_register(&spm_driver); +} +arch_initcall(qcom_spm_init); diff --git a/include/soc/qcom/spm.h b/include/soc/qcom/spm.h new file mode 100644 index 000000000000..4c7e5ac2583d --- /dev/null +++ b/include/soc/qcom/spm.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2011-2014, The Linux Foundation. All rights reserved. + * Copyright (c) 2014,2015, Linaro Ltd. + */ + +#ifndef __SPM_H__ +#define __SPM_H__ + +#include <linux/cpuidle.h> + +#define MAX_PMIC_DATA 2 +#define MAX_SEQ_DATA 64 + +enum pm_sleep_mode { + PM_SLEEP_MODE_STBY, + PM_SLEEP_MODE_RET, + PM_SLEEP_MODE_SPC, + PM_SLEEP_MODE_PC, + PM_SLEEP_MODE_NR, +}; + +struct spm_reg_data { + const u8 *reg_offset; + u32 spm_cfg; + u32 spm_dly; + u32 pmic_dly; + u32 pmic_data[MAX_PMIC_DATA]; + u8 seq[MAX_SEQ_DATA]; + u8 start_index[PM_SLEEP_MODE_NR]; +}; + +struct spm_driver_data { + void __iomem *reg_base; + const struct spm_reg_data *reg_data; +}; + +void spm_set_low_power_mode(struct spm_driver_data *drv, + enum pm_sleep_mode mode); + +#endif /* __SPM_H__ */

[v6,1/5] cpuidle: qcom_spm: Detach state machine from main SPM handling

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