| Message ID | 20210928162903.1104847-1-robdclark@gmail.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | drm/msm/dpu: Remove some nonsense | expand |
On 28/09/2021 19:28, Rob Clark wrote: > From: Rob Clark <robdclark@chromium.org> > > These aren't used. And if we add use for them later, we should probably > do something a bit more structured than string parsing. > > Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 ------ > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 8 -------- > 2 files changed, 14 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > index b131fd376192..e32dbb06aad1 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > @@ -958,12 +958,6 @@ static const struct dpu_perf_cfg sdm845_perf_data = { > .min_core_ib = 2400000, > .min_llcc_ib = 800000, > .min_dram_ib = 800000, > - .core_ib_ff = "6.0", > - .core_clk_ff = "1.0", > - .comp_ratio_rt = > - "NV12/5/1/1.23 AB24/5/1/1.23 XB24/5/1/1.23", > - .comp_ratio_nrt = > - "NV12/5/1/1.25 AB24/5/1/1.25 XB24/5/1/1.25", > .undersized_prefill_lines = 2, > .xtra_prefill_lines = 2, > .dest_scale_prefill_lines = 3, > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > index d2a945a27cfa..4ade44bbd37e 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > @@ -676,10 +676,6 @@ struct dpu_perf_cdp_cfg { > * @min_core_ib minimum mnoc ib vote in kbps > * @min_llcc_ib minimum llcc ib vote in kbps > * @min_dram_ib minimum dram ib vote in kbps > - * @core_ib_ff core instantaneous bandwidth fudge factor > - * @core_clk_ff core clock fudge factor > - * @comp_ratio_rt string of 0 or more of <fourcc>/<ven>/<mod>/<comp ratio> > - * @comp_ratio_nrt string of 0 or more of <fourcc>/<ven>/<mod>/<comp ratio> > * @undersized_prefill_lines undersized prefill in lines > * @xtra_prefill_lines extra prefill latency in lines > * @dest_scale_prefill_lines destination scaler latency in lines > @@ -702,10 +698,6 @@ struct dpu_perf_cfg { > u32 min_core_ib; > u32 min_llcc_ib; > u32 min_dram_ib; > - const char *core_ib_ff; > - const char *core_clk_ff; > - const char *comp_ratio_rt; > - const char *comp_ratio_nrt; > u32 undersized_prefill_lines; > u32 xtra_prefill_lines; > u32 dest_scale_prefill_lines; >
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index b131fd376192..e32dbb06aad1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -958,12 +958,6 @@ static const struct dpu_perf_cfg sdm845_perf_data = { .min_core_ib = 2400000, .min_llcc_ib = 800000, .min_dram_ib = 800000, - .core_ib_ff = "6.0", - .core_clk_ff = "1.0", - .comp_ratio_rt = - "NV12/5/1/1.23 AB24/5/1/1.23 XB24/5/1/1.23", - .comp_ratio_nrt = - "NV12/5/1/1.25 AB24/5/1/1.25 XB24/5/1/1.25", .undersized_prefill_lines = 2, .xtra_prefill_lines = 2, .dest_scale_prefill_lines = 3, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index d2a945a27cfa..4ade44bbd37e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -676,10 +676,6 @@ struct dpu_perf_cdp_cfg { * @min_core_ib minimum mnoc ib vote in kbps * @min_llcc_ib minimum llcc ib vote in kbps * @min_dram_ib minimum dram ib vote in kbps - * @core_ib_ff core instantaneous bandwidth fudge factor - * @core_clk_ff core clock fudge factor - * @comp_ratio_rt string of 0 or more of <fourcc>/<ven>/<mod>/<comp ratio> - * @comp_ratio_nrt string of 0 or more of <fourcc>/<ven>/<mod>/<comp ratio> * @undersized_prefill_lines undersized prefill in lines * @xtra_prefill_lines extra prefill latency in lines * @dest_scale_prefill_lines destination scaler latency in lines @@ -702,10 +698,6 @@ struct dpu_perf_cfg { u32 min_core_ib; u32 min_llcc_ib; u32 min_dram_ib; - const char *core_ib_ff; - const char *core_clk_ff; - const char *comp_ratio_rt; - const char *comp_ratio_nrt; u32 undersized_prefill_lines; u32 xtra_prefill_lines; u32 dest_scale_prefill_lines;