| Message ID | 20210930140002.308628-7-dmitry.baryshkov@linaro.org (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | drm/msm/dpu: cleanup plane state | expand |
On 2021-09-30 06:59, Dmitry Baryshkov wrote: > Scaler and pixel_ext configuration does not contain a long living > state, > it is used only during plane update, so remove these two fiels from fiels ---> fields > dpu_plane_state and allocate them on stack. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> While addressing the bugs reported by the smatch tool, I saw that pe is not being used at the moment. 412 static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_pipe *ctx, 413 struct dpu_hw_pipe_cfg *sspp, 414 struct dpu_hw_pixel_ext *pe, 415 void *scaler_cfg) 416 { 417 u32 idx; 418 struct dpu_hw_scaler3_cfg *scaler3_cfg = scaler_cfg; 419 420 (void)pe; 421 if (_sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx) || !sspp 422 || !scaler3_cfg || !ctx || !ctx->cap || !ctx->cap->sblk) 423 return; 424 425 dpu_hw_setup_scaler3(&ctx->hw, scaler3_cfg, idx, 426 ctx->cap->sblk->scaler_blk.version, 427 sspp->layout.format); 428 } As part of this change, can you please drop this? > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 59 ++++++++++------------- > drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 6 --- > 2 files changed, 26 insertions(+), 39 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > index 5288b5b824f8..4259c4ecde9b 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > @@ -542,14 +542,12 @@ static void _dpu_plane_setup_scaler3(struct > dpu_plane *pdpu, > struct dpu_plane_state *pstate, > uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h, > struct dpu_hw_scaler3_cfg *scale_cfg, > + struct dpu_hw_pixel_ext *pixel_ext, > const struct dpu_format *fmt, > uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v) > { > uint32_t i; > > - memset(scale_cfg, 0, sizeof(*scale_cfg)); > - memset(&pstate->pixel_ext, 0, sizeof(struct dpu_hw_pixel_ext)); > - > scale_cfg->phase_step_x[DPU_SSPP_COMP_0] = > mult_frac((1 << PHASE_STEP_SHIFT), src_w, dst_w); > scale_cfg->phase_step_y[DPU_SSPP_COMP_0] = > @@ -588,9 +586,9 @@ static void _dpu_plane_setup_scaler3(struct > dpu_plane *pdpu, > scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V; > } > > - pstate->pixel_ext.num_ext_pxls_top[i] = > + pixel_ext->num_ext_pxls_top[i] = > scale_cfg->src_height[i]; > - pstate->pixel_ext.num_ext_pxls_left[i] = > + pixel_ext->num_ext_pxls_left[i] = > scale_cfg->src_width[i]; > } > if (!(DPU_FORMAT_IS_YUV(fmt)) && (src_h == dst_h) > @@ -660,6 +658,11 @@ static void _dpu_plane_setup_scaler(struct > dpu_plane *pdpu, > struct dpu_hw_pipe_cfg *pipe_cfg) > { > const struct drm_format_info *info = > drm_format_info(fmt->base.pixel_format); > + struct dpu_hw_scaler3_cfg scaler3_cfg; > + struct dpu_hw_pixel_ext pixel_ext; > + > + memset(&scaler3_cfg, 0, sizeof(scaler3_cfg)); > + memset(&pixel_ext, 0, sizeof(pixel_ext)); > > /* don't chroma subsample if decimating */ > /* update scaler. calculate default config for QSEED3 */ > @@ -668,8 +671,23 @@ static void _dpu_plane_setup_scaler(struct > dpu_plane *pdpu, > drm_rect_height(&pipe_cfg->src_rect), > drm_rect_width(&pipe_cfg->dst_rect), > drm_rect_height(&pipe_cfg->dst_rect), > - &pstate->scaler3_cfg, fmt, > + &scaler3_cfg, &pixel_ext, fmt, > info->hsub, info->vsub); > + > + if (pdpu->pipe_hw->ops.setup_pe) > + pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw, > + &pixel_ext); > + > + /** > + * when programmed in multirect mode, scalar block will be > + * bypassed. Still we need to update alpha and bitwidth > + * ONLY for RECT0 > + */ > + if (pdpu->pipe_hw->ops.setup_scaler && > + pstate->multirect_index != DPU_SSPP_RECT_1) > + pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw, > + pipe_cfg, &pixel_ext, > + &scaler3_cfg); > } > > /** > @@ -710,7 +728,6 @@ static int _dpu_plane_color_fill(struct dpu_plane > *pdpu, > drm_rect_width(&pipe_cfg.dst_rect); > pipe_cfg.src_rect.y2 = > drm_rect_height(&pipe_cfg.dst_rect); > - _dpu_plane_setup_scaler(pdpu, pstate, fmt, true, &pipe_cfg); > > if (pdpu->pipe_hw->ops.setup_format) > pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, > @@ -722,15 +739,7 @@ static int _dpu_plane_color_fill(struct dpu_plane > *pdpu, > &pipe_cfg, > pstate->multirect_index); > > - if (pdpu->pipe_hw->ops.setup_pe) > - pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw, > - &pstate->pixel_ext); > - > - if (pdpu->pipe_hw->ops.setup_scaler && > - pstate->multirect_index != DPU_SSPP_RECT_1) > - pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw, > - &pipe_cfg, &pstate->pixel_ext, > - &pstate->scaler3_cfg); > + _dpu_plane_setup_scaler(pdpu, pstate, fmt, true, &pipe_cfg); > } > > return 0; > @@ -1122,8 +1131,6 @@ static void dpu_plane_sspp_atomic_update(struct > drm_plane *plane) > > pipe_cfg.dst_rect = state->dst; > > - _dpu_plane_setup_scaler(pdpu, pstate, fmt, false, &pipe_cfg); > - > /* override for color fill */ > if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) { > /* skip remaining processing on color fill */ > @@ -1136,21 +1143,7 @@ static void dpu_plane_sspp_atomic_update(struct > drm_plane *plane) > pstate->multirect_index); > } > > - if (pdpu->pipe_hw->ops.setup_pe && > - (pstate->multirect_index != DPU_SSPP_RECT_1)) > - pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw, > - &pstate->pixel_ext); > - > - /** > - * when programmed in multirect mode, scalar block will be > - * bypassed. Still we need to update alpha and bitwidth > - * ONLY for RECT0 > - */ > - if (pdpu->pipe_hw->ops.setup_scaler && > - pstate->multirect_index != DPU_SSPP_RECT_1) > - pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw, > - &pipe_cfg, &pstate->pixel_ext, > - &pstate->scaler3_cfg); > + _dpu_plane_setup_scaler(pdpu, pstate, fmt, false, &pipe_cfg); > > if (pdpu->pipe_hw->ops.setup_multirect) > pdpu->pipe_hw->ops.setup_multirect( > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h > b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h > index 34e03ac05f4a..087194be3c22 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h > @@ -23,8 +23,6 @@ > * @multirect_index: index of the rectangle of SSPP > * @multirect_mode: parallel or time multiplex multirect mode > * @pending: whether the current update is still pending > - * @scaler3_cfg: configuration data for scaler3 > - * @pixel_ext: configuration data for pixel extensions > * @cdp_cfg: CDP configuration > * @plane_fetch_bw: calculated BW per plane > * @plane_clk: calculated clk per plane > @@ -38,10 +36,6 @@ struct dpu_plane_state { > uint32_t multirect_mode; > bool pending; > > - /* scaler configuration */ > - struct dpu_hw_scaler3_cfg scaler3_cfg; > - struct dpu_hw_pixel_ext pixel_ext; > - > struct dpu_hw_pipe_cdp_cfg cdp_cfg; > u64 plane_fetch_bw; > u64 plane_clk;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 5288b5b824f8..4259c4ecde9b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -542,14 +542,12 @@ static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu, struct dpu_plane_state *pstate, uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h, struct dpu_hw_scaler3_cfg *scale_cfg, + struct dpu_hw_pixel_ext *pixel_ext, const struct dpu_format *fmt, uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v) { uint32_t i; - memset(scale_cfg, 0, sizeof(*scale_cfg)); - memset(&pstate->pixel_ext, 0, sizeof(struct dpu_hw_pixel_ext)); - scale_cfg->phase_step_x[DPU_SSPP_COMP_0] = mult_frac((1 << PHASE_STEP_SHIFT), src_w, dst_w); scale_cfg->phase_step_y[DPU_SSPP_COMP_0] = @@ -588,9 +586,9 @@ static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu, scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V; } - pstate->pixel_ext.num_ext_pxls_top[i] = + pixel_ext->num_ext_pxls_top[i] = scale_cfg->src_height[i]; - pstate->pixel_ext.num_ext_pxls_left[i] = + pixel_ext->num_ext_pxls_left[i] = scale_cfg->src_width[i]; } if (!(DPU_FORMAT_IS_YUV(fmt)) && (src_h == dst_h) @@ -660,6 +658,11 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu, struct dpu_hw_pipe_cfg *pipe_cfg) { const struct drm_format_info *info = drm_format_info(fmt->base.pixel_format); + struct dpu_hw_scaler3_cfg scaler3_cfg; + struct dpu_hw_pixel_ext pixel_ext; + + memset(&scaler3_cfg, 0, sizeof(scaler3_cfg)); + memset(&pixel_ext, 0, sizeof(pixel_ext)); /* don't chroma subsample if decimating */ /* update scaler. calculate default config for QSEED3 */ @@ -668,8 +671,23 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu, drm_rect_height(&pipe_cfg->src_rect), drm_rect_width(&pipe_cfg->dst_rect), drm_rect_height(&pipe_cfg->dst_rect), - &pstate->scaler3_cfg, fmt, + &scaler3_cfg, &pixel_ext, fmt, info->hsub, info->vsub); + + if (pdpu->pipe_hw->ops.setup_pe) + pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw, + &pixel_ext); + + /** + * when programmed in multirect mode, scalar block will be + * bypassed. Still we need to update alpha and bitwidth + * ONLY for RECT0 + */ + if (pdpu->pipe_hw->ops.setup_scaler && + pstate->multirect_index != DPU_SSPP_RECT_1) + pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw, + pipe_cfg, &pixel_ext, + &scaler3_cfg); } /** @@ -710,7 +728,6 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu, drm_rect_width(&pipe_cfg.dst_rect); pipe_cfg.src_rect.y2 = drm_rect_height(&pipe_cfg.dst_rect); - _dpu_plane_setup_scaler(pdpu, pstate, fmt, true, &pipe_cfg); if (pdpu->pipe_hw->ops.setup_format) pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, @@ -722,15 +739,7 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu, &pipe_cfg, pstate->multirect_index); - if (pdpu->pipe_hw->ops.setup_pe) - pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw, - &pstate->pixel_ext); - - if (pdpu->pipe_hw->ops.setup_scaler && - pstate->multirect_index != DPU_SSPP_RECT_1) - pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw, - &pipe_cfg, &pstate->pixel_ext, - &pstate->scaler3_cfg); + _dpu_plane_setup_scaler(pdpu, pstate, fmt, true, &pipe_cfg); } return 0; @@ -1122,8 +1131,6 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) pipe_cfg.dst_rect = state->dst; - _dpu_plane_setup_scaler(pdpu, pstate, fmt, false, &pipe_cfg); - /* override for color fill */ if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) { /* skip remaining processing on color fill */ @@ -1136,21 +1143,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) pstate->multirect_index); } - if (pdpu->pipe_hw->ops.setup_pe && - (pstate->multirect_index != DPU_SSPP_RECT_1)) - pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw, - &pstate->pixel_ext); - - /** - * when programmed in multirect mode, scalar block will be - * bypassed. Still we need to update alpha and bitwidth - * ONLY for RECT0 - */ - if (pdpu->pipe_hw->ops.setup_scaler && - pstate->multirect_index != DPU_SSPP_RECT_1) - pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw, - &pipe_cfg, &pstate->pixel_ext, - &pstate->scaler3_cfg); + _dpu_plane_setup_scaler(pdpu, pstate, fmt, false, &pipe_cfg); if (pdpu->pipe_hw->ops.setup_multirect) pdpu->pipe_hw->ops.setup_multirect( diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h index 34e03ac05f4a..087194be3c22 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h @@ -23,8 +23,6 @@ * @multirect_index: index of the rectangle of SSPP * @multirect_mode: parallel or time multiplex multirect mode * @pending: whether the current update is still pending - * @scaler3_cfg: configuration data for scaler3 - * @pixel_ext: configuration data for pixel extensions * @cdp_cfg: CDP configuration * @plane_fetch_bw: calculated BW per plane * @plane_clk: calculated clk per plane @@ -38,10 +36,6 @@ struct dpu_plane_state { uint32_t multirect_mode; bool pending; - /* scaler configuration */ - struct dpu_hw_scaler3_cfg scaler3_cfg; - struct dpu_hw_pixel_ext pixel_ext; - struct dpu_hw_pipe_cdp_cfg cdp_cfg; u64 plane_fetch_bw; u64 plane_clk;
Scaler and pixel_ext configuration does not contain a long living state, it is used only during plane update, so remove these two fiels from dpu_plane_state and allocate them on stack. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 59 ++++++++++------------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 6 --- 2 files changed, 26 insertions(+), 39 deletions(-)