| Message ID | 20211011094822.1580122-1-vladimir.zapolskiy@linaro.org (mailing list archive) |
|---|---|
| State | Accepted |
| Headers | show |
| Series | dts: qcom: msm8996: Add device tree entries to support crypto engine | expand |
On 10/11/21 5:48 AM, Vladimir Zapolskiy wrote: > The change adds description of Qualcomm crypto engine controller and > BAM associated with it. The change is inspired by commit 3e482859f1ef > ("dts: qcom: sdm845: Add dt entries to support crypto engine.") > > While performance of cryptographic algorithms executed on QCE is lower > than e.g. ones tinkered for ARM NEON, the offloaded execution would > make sense: > > # cryptsetup benchmark | grep aes > aes-cbc 128b 71.0 MiB/s 71.9 MiB/s > aes-cbc 256b 62.4 MiB/s 62.4 MiB/s > aes-xts 256b 70.7 MiB/s 70.8 MiB/s > aes-xts 512b 62.0 MiB/s 63.3 MiB/s > > Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> > Cc: Thara Gopinath <thara.gopinath@linaro.org> > --- > arch/arm64/boot/dts/qcom/msm8996.dtsi | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi > index 52df22ab3f6a..a03cbeb58246 100644 > --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi > @@ -705,6 +705,28 @@ tsens1: thermal-sensor@4ad000 { > #thermal-sensor-cells = <1>; > }; > > + cryptobam: dma@644000 { > + compatible = "qcom,bam-v1.7.0"; > + reg = <0x00644000 0x24000>; > + interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&gcc GCC_CE1_CLK>; > + clock-names = "bam_clk"; > + #dma-cells = <1>; > + qcom,ee = <0>; > + qcom,controlled-remotely = <1>; > + }; > + > + crypto: crypto@67a000 { > + compatible = "qcom,crypto-v5.4"; > + reg = <0x0067a000 0x6000>; > + clocks = <&gcc GCC_CE1_AHB_CLK>, > + <&gcc GCC_CE1_AXI_CLK>, > + <&gcc GCC_CE1_CLK>; > + clock-names = "iface", "bus", "core"; > + dmas = <&cryptobam 6>, <&cryptobam 7>; > + dma-names = "rx", "tx"; > + }; > + Hi Vlad, Hi Vladimir, I am surprised that you don't need to specify iommu to get this working. Everything else looks okay to me, though I don't have the h/w to test. So, Acked-by: Thara Gopinath <thara.gopinath@linaro.org> > tcsr_mutex_regs: syscon@740000 { > compatible = "syscon"; > reg = <0x00740000 0x40000>; >
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 52df22ab3f6a..a03cbeb58246 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -705,6 +705,28 @@ tsens1: thermal-sensor@4ad000 { #thermal-sensor-cells = <1>; }; + cryptobam: dma@644000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x00644000 0x24000>; + interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_CE1_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely = <1>; + }; + + crypto: crypto@67a000 { + compatible = "qcom,crypto-v5.4"; + reg = <0x0067a000 0x6000>; + clocks = <&gcc GCC_CE1_AHB_CLK>, + <&gcc GCC_CE1_AXI_CLK>, + <&gcc GCC_CE1_CLK>; + clock-names = "iface", "bus", "core"; + dmas = <&cryptobam 6>, <&cryptobam 7>; + dma-names = "rx", "tx"; + }; + tcsr_mutex_regs: syscon@740000 { compatible = "syscon"; reg = <0x00740000 0x40000>;
The change adds description of Qualcomm crypto engine controller and BAM associated with it. The change is inspired by commit 3e482859f1ef ("dts: qcom: sdm845: Add dt entries to support crypto engine.") While performance of cryptographic algorithms executed on QCE is lower than e.g. ones tinkered for ARM NEON, the offloaded execution would make sense: # cryptsetup benchmark | grep aes aes-cbc 128b 71.0 MiB/s 71.9 MiB/s aes-cbc 256b 62.4 MiB/s 62.4 MiB/s aes-xts 256b 70.7 MiB/s 70.8 MiB/s aes-xts 512b 62.0 MiB/s 63.3 MiB/s Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Cc: Thara Gopinath <thara.gopinath@linaro.org> --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)