| Message ID | 20211013105541.68045-15-bhupesh.sharma@linaro.org (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | Enable Qualcomm Crypto Engine on sm8250 | expand |
Hi Bhupesh, On 10/13/21 1:55 PM, Bhupesh Sharma wrote: > From: Thara Gopinath <thara.gopinath@linaro.org> > > Crypto engine on certain Snapdragon processors like sm8150, sm8250, sm8350 > etc. requires interconnect path between the engine and memory to be > explicitly enabled and bandwidth set prior to any operations. Add support > in the qce core to enable the interconnect path appropriately. > > Cc: Bjorn Andersson <bjorn.andersson@linaro.org> > Cc: Rob Herring <robh+dt@kernel.org> > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> > [Make header file inclusion alphabetical] > Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org> > --- > drivers/crypto/qce/core.c | 35 ++++++++++++++++++++++++++++------- > drivers/crypto/qce/core.h | 1 + > 2 files changed, 29 insertions(+), 7 deletions(-) > > diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c > index d3780be44a76..033c7278aa5d 100644 > --- a/drivers/crypto/qce/core.c > +++ b/drivers/crypto/qce/core.c > @@ -5,6 +5,7 @@ > > #include <linux/clk.h> > #include <linux/dma-mapping.h> > +#include <linux/interconnect.h> > #include <linux/interrupt.h> > #include <linux/module.h> > #include <linux/mod_devicetable.h> > @@ -22,6 +23,8 @@ > #define QCE_MAJOR_VERSION5 0x05 > #define QCE_QUEUE_LENGTH 1 > > +#define QCE_DEFAULT_MEM_BANDWIDTH 393600 > + > static const struct qce_algo_ops *qce_ops[] = { > #ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER > &skcipher_ops, > @@ -206,21 +209,35 @@ static int qce_crypto_probe(struct platform_device *pdev) > if (ret < 0) > return ret; > > + qce->mem_path = of_icc_get(qce->dev, "memory"); Please consider to use devm_of_icc_get() here also. > + if (IS_ERR(qce->mem_path)) > + return PTR_ERR(qce->mem_path); > + > qce->core = devm_clk_get(qce->dev, "core"); > - if (IS_ERR(qce->core)) > - return PTR_ERR(qce->core); > + if (IS_ERR(qce->core)) { > + ret = PTR_ERR(qce->core); > + goto err_mem_path_put; > + } > > qce->iface = devm_clk_get(qce->dev, "iface"); > - if (IS_ERR(qce->iface)) > - return PTR_ERR(qce->iface); > + if (IS_ERR(qce->iface)) { > + ret = PTR_ERR(qce->iface); > + goto err_mem_path_put; > + } > > qce->bus = devm_clk_get(qce->dev, "bus"); > - if (IS_ERR(qce->bus)) > - return PTR_ERR(qce->bus); > + if (IS_ERR(qce->bus)) { > + ret = PTR_ERR(qce->bus); > + goto err_mem_path_put; > + } > + > + ret = icc_set_bw(qce->mem_path, QCE_DEFAULT_MEM_BANDWIDTH, QCE_DEFAULT_MEM_BANDWIDTH); > + if (ret) > + goto err_mem_path_put; > > ret = clk_prepare_enable(qce->core); > if (ret) > - return ret; > + goto err_mem_path_disable; > > ret = clk_prepare_enable(qce->iface); > if (ret) > @@ -260,6 +277,10 @@ static int qce_crypto_probe(struct platform_device *pdev) > clk_disable_unprepare(qce->iface); > err_clks_core: > clk_disable_unprepare(qce->core); > +err_mem_path_disable: > + icc_set_bw(qce->mem_path, 0, 0); > +err_mem_path_put: > + icc_put(qce->mem_path); > return ret; > } > > diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h > index 085774cdf641..228fcd69ec51 100644 > --- a/drivers/crypto/qce/core.h > +++ b/drivers/crypto/qce/core.h > @@ -35,6 +35,7 @@ struct qce_device { > void __iomem *base; > struct device *dev; > struct clk *core, *iface, *bus; > + struct icc_path *mem_path; > struct qce_dma_data dma; > int burst_size; > unsigned int pipe_pair_id; > -- Best wishes, Vladimir
Hi Vladimir, On Thu, 14 Oct 2021 at 00:49, Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> wrote: > > Hi Bhupesh, > > On 10/13/21 1:55 PM, Bhupesh Sharma wrote: > > From: Thara Gopinath <thara.gopinath@linaro.org> > > > > Crypto engine on certain Snapdragon processors like sm8150, sm8250, sm8350 > > etc. requires interconnect path between the engine and memory to be > > explicitly enabled and bandwidth set prior to any operations. Add support > > in the qce core to enable the interconnect path appropriately. > > > > Cc: Bjorn Andersson <bjorn.andersson@linaro.org> > > Cc: Rob Herring <robh+dt@kernel.org> > > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> > > [Make header file inclusion alphabetical] > > Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org> > > --- > > drivers/crypto/qce/core.c | 35 ++++++++++++++++++++++++++++------- > > drivers/crypto/qce/core.h | 1 + > > 2 files changed, 29 insertions(+), 7 deletions(-) > > > > diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c > > index d3780be44a76..033c7278aa5d 100644 > > --- a/drivers/crypto/qce/core.c > > +++ b/drivers/crypto/qce/core.c > > @@ -5,6 +5,7 @@ > > > > #include <linux/clk.h> > > #include <linux/dma-mapping.h> > > +#include <linux/interconnect.h> > > #include <linux/interrupt.h> > > #include <linux/module.h> > > #include <linux/mod_devicetable.h> > > @@ -22,6 +23,8 @@ > > #define QCE_MAJOR_VERSION5 0x05 > > #define QCE_QUEUE_LENGTH 1 > > > > +#define QCE_DEFAULT_MEM_BANDWIDTH 393600 > > + > > static const struct qce_algo_ops *qce_ops[] = { > > #ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER > > &skcipher_ops, > > @@ -206,21 +209,35 @@ static int qce_crypto_probe(struct platform_device *pdev) > > if (ret < 0) > > return ret; > > > > + qce->mem_path = of_icc_get(qce->dev, "memory"); > > Please consider to use devm_of_icc_get() here also. Thanks, I will fix this in the v5. Regards, Bhupesh > > + if (IS_ERR(qce->mem_path)) > > + return PTR_ERR(qce->mem_path); > > + > > qce->core = devm_clk_get(qce->dev, "core"); > > - if (IS_ERR(qce->core)) > > - return PTR_ERR(qce->core); > > + if (IS_ERR(qce->core)) { > > + ret = PTR_ERR(qce->core); > > + goto err_mem_path_put; > > + } > > > > qce->iface = devm_clk_get(qce->dev, "iface"); > > - if (IS_ERR(qce->iface)) > > - return PTR_ERR(qce->iface); > > + if (IS_ERR(qce->iface)) { > > + ret = PTR_ERR(qce->iface); > > + goto err_mem_path_put; > > + } > > > > qce->bus = devm_clk_get(qce->dev, "bus"); > > - if (IS_ERR(qce->bus)) > > - return PTR_ERR(qce->bus); > > + if (IS_ERR(qce->bus)) { > > + ret = PTR_ERR(qce->bus); > > + goto err_mem_path_put; > > + } > > + > > + ret = icc_set_bw(qce->mem_path, QCE_DEFAULT_MEM_BANDWIDTH, QCE_DEFAULT_MEM_BANDWIDTH); > > + if (ret) > > + goto err_mem_path_put; > > > > ret = clk_prepare_enable(qce->core); > > if (ret) > > - return ret; > > + goto err_mem_path_disable; > > > > ret = clk_prepare_enable(qce->iface); > > if (ret) > > @@ -260,6 +277,10 @@ static int qce_crypto_probe(struct platform_device *pdev) > > clk_disable_unprepare(qce->iface); > > err_clks_core: > > clk_disable_unprepare(qce->core); > > +err_mem_path_disable: > > + icc_set_bw(qce->mem_path, 0, 0); > > +err_mem_path_put: > > + icc_put(qce->mem_path); > > return ret; > > } > > > > diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h > > index 085774cdf641..228fcd69ec51 100644 > > --- a/drivers/crypto/qce/core.h > > +++ b/drivers/crypto/qce/core.h > > @@ -35,6 +35,7 @@ struct qce_device { > > void __iomem *base; > > struct device *dev; > > struct clk *core, *iface, *bus; > > + struct icc_path *mem_path; > > struct qce_dma_data dma; > > int burst_size; > > unsigned int pipe_pair_id; > > > > -- > Best wishes, > Vladimir
diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c index d3780be44a76..033c7278aa5d 100644 --- a/drivers/crypto/qce/core.c +++ b/drivers/crypto/qce/core.c @@ -5,6 +5,7 @@ #include <linux/clk.h> #include <linux/dma-mapping.h> +#include <linux/interconnect.h> #include <linux/interrupt.h> #include <linux/module.h> #include <linux/mod_devicetable.h> @@ -22,6 +23,8 @@ #define QCE_MAJOR_VERSION5 0x05 #define QCE_QUEUE_LENGTH 1 +#define QCE_DEFAULT_MEM_BANDWIDTH 393600 + static const struct qce_algo_ops *qce_ops[] = { #ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER &skcipher_ops, @@ -206,21 +209,35 @@ static int qce_crypto_probe(struct platform_device *pdev) if (ret < 0) return ret; + qce->mem_path = of_icc_get(qce->dev, "memory"); + if (IS_ERR(qce->mem_path)) + return PTR_ERR(qce->mem_path); + qce->core = devm_clk_get(qce->dev, "core"); - if (IS_ERR(qce->core)) - return PTR_ERR(qce->core); + if (IS_ERR(qce->core)) { + ret = PTR_ERR(qce->core); + goto err_mem_path_put; + } qce->iface = devm_clk_get(qce->dev, "iface"); - if (IS_ERR(qce->iface)) - return PTR_ERR(qce->iface); + if (IS_ERR(qce->iface)) { + ret = PTR_ERR(qce->iface); + goto err_mem_path_put; + } qce->bus = devm_clk_get(qce->dev, "bus"); - if (IS_ERR(qce->bus)) - return PTR_ERR(qce->bus); + if (IS_ERR(qce->bus)) { + ret = PTR_ERR(qce->bus); + goto err_mem_path_put; + } + + ret = icc_set_bw(qce->mem_path, QCE_DEFAULT_MEM_BANDWIDTH, QCE_DEFAULT_MEM_BANDWIDTH); + if (ret) + goto err_mem_path_put; ret = clk_prepare_enable(qce->core); if (ret) - return ret; + goto err_mem_path_disable; ret = clk_prepare_enable(qce->iface); if (ret) @@ -260,6 +277,10 @@ static int qce_crypto_probe(struct platform_device *pdev) clk_disable_unprepare(qce->iface); err_clks_core: clk_disable_unprepare(qce->core); +err_mem_path_disable: + icc_set_bw(qce->mem_path, 0, 0); +err_mem_path_put: + icc_put(qce->mem_path); return ret; } diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h index 085774cdf641..228fcd69ec51 100644 --- a/drivers/crypto/qce/core.h +++ b/drivers/crypto/qce/core.h @@ -35,6 +35,7 @@ struct qce_device { void __iomem *base; struct device *dev; struct clk *core, *iface, *bus; + struct icc_path *mem_path; struct qce_dma_data dma; int burst_size; unsigned int pipe_pair_id;