From patchwork Thu Oct 21 18:01:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jack Pham X-Patchwork-Id: 12576003 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA73FC433F5 for ; Thu, 21 Oct 2021 18:01:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CAC216121F for ; Thu, 21 Oct 2021 18:01:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232375AbhJUSEL (ORCPT ); Thu, 21 Oct 2021 14:04:11 -0400 Received: from so254-9.mailgun.net ([198.61.254.9]:48886 "EHLO so254-9.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232300AbhJUSEK (ORCPT ); Thu, 21 Oct 2021 14:04:10 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1634839314; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=wPke1kVExHHKxzuSn8tsmK/QATxLQG/Xj0V+uR+hkzg=; b=pfnEGEprHKGgPyz2vL6S1lMKEbMgIa65mwT08s+rm77cTw3Xx9MOUd5lkIOjiEpOb/IAAmsi nl6KzYPASSBIaiiN7bd0zN8A7+0nwVQrNAsTScKrs6vGNC1hCKkFtERWxG594bkRw/CvkuxB F5KsYJqhl6rh/A8CHUE0UrAIPNI= X-Mailgun-Sending-Ip: 198.61.254.9 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n01.prod.us-west-2.postgun.com with SMTP id 6171ab0167f107c611159816 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Thu, 21 Oct 2021 18:01:37 GMT Sender: jackp=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 91B8AC43460; Thu, 21 Oct 2021 18:01:37 +0000 (UTC) Received: from jackp-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jackp) by smtp.codeaurora.org (Postfix) with ESMTPSA id D2728C4338F; Thu, 21 Oct 2021 18:01:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.codeaurora.org D2728C4338F Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=codeaurora.org From: Jack Pham To: Greg Kroah-Hartman , Felipe Balbi , Thinh Nguyen , Wesley Cheng Cc: linux-usb@vger.kernel.org, linux-arm-msm@vger.kernel.org, Jack Pham Subject: [PATCH v3 2/2] usb: dwc3: Align DWC3_EP_* flag macros Date: Thu, 21 Oct 2021 11:01:29 -0700 Message-Id: <20211021180129.27938-2-jackp@codeaurora.org> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20211021180129.27938-1-jackp@codeaurora.org> References: <20211021180129.27938-1-jackp@codeaurora.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Fix the DWC3_EP_* flag macros so that the definitions are all lined up on the same tab column for consistent style. No functional change. Signed-off-by: Jack Pham --- v3: New patch drivers/usb/dwc3/core.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 0c100901a784..054795d78b68 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -711,13 +711,13 @@ struct dwc3_ep { u32 saved_state; unsigned int flags; -#define DWC3_EP_ENABLED BIT(0) -#define DWC3_EP_STALL BIT(1) -#define DWC3_EP_WEDGE BIT(2) -#define DWC3_EP_TRANSFER_STARTED BIT(3) -#define DWC3_EP_END_TRANSFER_PENDING BIT(4) -#define DWC3_EP_PENDING_REQUEST BIT(5) -#define DWC3_EP_DELAY_START BIT(6) +#define DWC3_EP_ENABLED BIT(0) +#define DWC3_EP_STALL BIT(1) +#define DWC3_EP_WEDGE BIT(2) +#define DWC3_EP_TRANSFER_STARTED BIT(3) +#define DWC3_EP_END_TRANSFER_PENDING BIT(4) +#define DWC3_EP_PENDING_REQUEST BIT(5) +#define DWC3_EP_DELAY_START BIT(6) #define DWC3_EP_WAIT_TRANSFER_COMPLETE BIT(7) #define DWC3_EP_IGNORE_NEXT_NOSTREAM BIT(8) #define DWC3_EP_FORCE_RESTART_STREAM BIT(9) @@ -726,7 +726,7 @@ struct dwc3_ep { #define DWC3_EP_TXFIFO_RESIZED BIT(12) /* This last one is specific to EP0 */ -#define DWC3_EP0_DIR_IN BIT(31) +#define DWC3_EP0_DIR_IN BIT(31) /* * IMPORTANT: we *know* we have 256 TRBs in our @trb_pool, so we will