| Message ID | 20211116062256.2417186-10-vkoul@kernel.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | drm/msm: Add Display Stream Compression Support | expand |
On 16/11/2021 09:22, Vinod Koul wrote: > For DSC to work we typically need a 2,2,1 configuration. This should > suffice for resolutions up to 4k. For more resolutions like 8k this won't > work. > > Also, it is better to use 2 LMs and DSC instances as half width results > in lesser power consumption as compared to single LM, DSC at full width. > > The panel has been tested only with 2,2,1 configuration, so for > now we blindly create 2,2,1 topology when DSC is enabled > > Co-developed-by: Abhinav Kumar <abhinavk@codeaurora.org> > Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org> > Signed-off-by: Vinod Koul <vkoul@kernel.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 18 ++++++++++++++++++ > drivers/gpu/drm/msm/msm_drv.h | 2 ++ > 2 files changed, 20 insertions(+) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > index f2ff8a504918..12f58de88ac7 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > @@ -533,6 +533,8 @@ static struct msm_display_topology dpu_encoder_get_topology( > struct drm_display_mode *mode) > { > struct msm_display_topology topology = {0}; > + struct drm_encoder *drm_enc; > + struct msm_drm_private *priv; > int i, intf_count = 0; > > for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++) > @@ -567,8 +569,24 @@ static struct msm_display_topology dpu_encoder_get_topology( > topology.num_enc = 0; > topology.num_intf = intf_count; > > + drm_enc = &dpu_enc->base; > + priv = drm_enc->dev->dev_private; > + if (priv && priv->dsc) { > + /* In case of Display Stream Compression DSC, we would use > + * 2 encoders, 2 line mixers and 1 interface > + * this is power optimal and can drive up to (including) 4k > + * screens > + */ > + topology.num_enc = 2; > + topology.num_dsc = 2; > + topology.num_intf = 1; > + topology.num_lm = 2; > + priv->dsc->dsc_mask = BIT(0) | BIT(1); dsc_mask is still hardcoded here. We should use DSC indices returned from RM. > + } > + > return topology; > } > + > static int dpu_encoder_virt_atomic_check( > struct drm_encoder *drm_enc, > struct drm_crtc_state *crtc_state, > diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h > index c4a588ad226e..d6b25d77700e 100644 > --- a/drivers/gpu/drm/msm/msm_drv.h > +++ b/drivers/gpu/drm/msm/msm_drv.h > @@ -103,12 +103,14 @@ enum msm_event_wait { > * @num_enc: number of compression encoder blocks used > * @num_intf: number of interfaces the panel is mounted on > * @num_dspp: number of dspp blocks used > + * @num_dsc: number of Display Stream Compression (DSC) blocks used > */ > struct msm_display_topology { > u32 num_lm; > u32 num_enc; > u32 num_intf; > u32 num_dspp; > + u32 num_dsc; > }; > > /** >
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index f2ff8a504918..12f58de88ac7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -533,6 +533,8 @@ static struct msm_display_topology dpu_encoder_get_topology( struct drm_display_mode *mode) { struct msm_display_topology topology = {0}; + struct drm_encoder *drm_enc; + struct msm_drm_private *priv; int i, intf_count = 0; for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++) @@ -567,8 +569,24 @@ static struct msm_display_topology dpu_encoder_get_topology( topology.num_enc = 0; topology.num_intf = intf_count; + drm_enc = &dpu_enc->base; + priv = drm_enc->dev->dev_private; + if (priv && priv->dsc) { + /* In case of Display Stream Compression DSC, we would use + * 2 encoders, 2 line mixers and 1 interface + * this is power optimal and can drive up to (including) 4k + * screens + */ + topology.num_enc = 2; + topology.num_dsc = 2; + topology.num_intf = 1; + topology.num_lm = 2; + priv->dsc->dsc_mask = BIT(0) | BIT(1); + } + return topology; } + static int dpu_encoder_virt_atomic_check( struct drm_encoder *drm_enc, struct drm_crtc_state *crtc_state, diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index c4a588ad226e..d6b25d77700e 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -103,12 +103,14 @@ enum msm_event_wait { * @num_enc: number of compression encoder blocks used * @num_intf: number of interfaces the panel is mounted on * @num_dspp: number of dspp blocks used + * @num_dsc: number of Display Stream Compression (DSC) blocks used */ struct msm_display_topology { u32 num_lm; u32 num_enc; u32 num_intf; u32 num_dspp; + u32 num_dsc; }; /**