| Message ID | 20211208083423.22037-4-marijn.suijten@somainline.org (mailing list archive) |
|---|---|
| State | Accepted |
| Headers | show |
| Series | firmware: qcom: scm: Add IOMMU pool size and | expand |
On 12/8/21 2:34 AM, Marijn Suijten wrote: > From: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> > > Add a function to change the IOMMU pagetable addressing to > AArch32 LPAE or AArch64. If doing that, then this must be > done for each IOMMU context (not necessarily at the same time). > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> > [Marijn: ported from 5.3 to the unified architecture in 5.11] > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Are there no users of this function? -Alex > --- > drivers/firmware/qcom_scm.c | 16 ++++++++++++++++ > drivers/firmware/qcom_scm.h | 1 + > include/linux/qcom_scm.h | 1 + > 3 files changed, 18 insertions(+) > > diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c > index d5a9ba15e2ba..6f7096120023 100644 > --- a/drivers/firmware/qcom_scm.c > +++ b/drivers/firmware/qcom_scm.c > @@ -1140,6 +1140,22 @@ int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp) > } > EXPORT_SYMBOL(qcom_scm_hdcp_req); > > +int qcom_scm_iommu_set_pt_format(u32 sec_id, u32 ctx_num, u32 pt_fmt) > +{ > + struct qcom_scm_desc desc = { > + .svc = QCOM_SCM_SVC_SMMU_PROGRAM, > + .cmd = QCOM_SCM_SMMU_PT_FORMAT, > + .arginfo = QCOM_SCM_ARGS(3), > + .args[0] = sec_id, > + .args[1] = ctx_num, > + .args[2] = pt_fmt, /* 0: LPAE AArch32 - 1: AArch64 */ > + .owner = ARM_SMCCC_OWNER_SIP, > + }; > + > + return qcom_scm_call(__scm->dev, &desc, NULL); > +} > +EXPORT_SYMBOL(qcom_scm_iommu_set_pt_format); > + > int qcom_scm_qsmmu500_wait_safe_toggle(bool en) > { > struct qcom_scm_desc desc = { > diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h > index bb627941702b..a348f2c214e5 100644 > --- a/drivers/firmware/qcom_scm.h > +++ b/drivers/firmware/qcom_scm.h > @@ -120,6 +120,7 @@ extern int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc, > #define QCOM_SCM_LMH_LIMIT_DCVSH 0x10 > > #define QCOM_SCM_SVC_SMMU_PROGRAM 0x15 > +#define QCOM_SCM_SMMU_PT_FORMAT 0x01 > #define QCOM_SCM_SMMU_CONFIG_ERRATA1 0x03 > #define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL 0x02 > > diff --git a/include/linux/qcom_scm.h b/include/linux/qcom_scm.h > index 8a065f8660c1..ca4a88d7cbdc 100644 > --- a/include/linux/qcom_scm.h > +++ b/include/linux/qcom_scm.h > @@ -108,6 +108,7 @@ extern bool qcom_scm_hdcp_available(void); > extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, > u32 *resp); > > +extern int qcom_scm_iommu_set_pt_format(u32 sec_id, u32 ctx_num, u32 pt_fmt); > extern int qcom_scm_qsmmu500_wait_safe_toggle(bool en); > > extern int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val, >
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index d5a9ba15e2ba..6f7096120023 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -1140,6 +1140,22 @@ int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp) } EXPORT_SYMBOL(qcom_scm_hdcp_req); +int qcom_scm_iommu_set_pt_format(u32 sec_id, u32 ctx_num, u32 pt_fmt) +{ + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_SMMU_PROGRAM, + .cmd = QCOM_SCM_SMMU_PT_FORMAT, + .arginfo = QCOM_SCM_ARGS(3), + .args[0] = sec_id, + .args[1] = ctx_num, + .args[2] = pt_fmt, /* 0: LPAE AArch32 - 1: AArch64 */ + .owner = ARM_SMCCC_OWNER_SIP, + }; + + return qcom_scm_call(__scm->dev, &desc, NULL); +} +EXPORT_SYMBOL(qcom_scm_iommu_set_pt_format); + int qcom_scm_qsmmu500_wait_safe_toggle(bool en) { struct qcom_scm_desc desc = { diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h index bb627941702b..a348f2c214e5 100644 --- a/drivers/firmware/qcom_scm.h +++ b/drivers/firmware/qcom_scm.h @@ -120,6 +120,7 @@ extern int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc, #define QCOM_SCM_LMH_LIMIT_DCVSH 0x10 #define QCOM_SCM_SVC_SMMU_PROGRAM 0x15 +#define QCOM_SCM_SMMU_PT_FORMAT 0x01 #define QCOM_SCM_SMMU_CONFIG_ERRATA1 0x03 #define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL 0x02 diff --git a/include/linux/qcom_scm.h b/include/linux/qcom_scm.h index 8a065f8660c1..ca4a88d7cbdc 100644 --- a/include/linux/qcom_scm.h +++ b/include/linux/qcom_scm.h @@ -108,6 +108,7 @@ extern bool qcom_scm_hdcp_available(void); extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp); +extern int qcom_scm_iommu_set_pt_format(u32 sec_id, u32 ctx_num, u32 pt_fmt); extern int qcom_scm_qsmmu500_wait_safe_toggle(bool en); extern int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val,