| Message ID | 20211208175430.1333594-7-dmitry.baryshkov@linaro.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [01/11] clk: qcom: gpucc-sdm660: get rid of the test clock | expand |
On 2021-12-08 20:54:25, Dmitry Baryshkov wrote: > If all parents are specified as clk_hw, we can use parent_hws instead of > parent_data. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> > --- > drivers/clk/qcom/camcc-sc7180.c | 156 ++++++++++++++++---------------- > 1 file changed, 79 insertions(+), 77 deletions(-) > > diff --git a/drivers/clk/qcom/camcc-sc7180.c b/drivers/clk/qcom/camcc-sc7180.c > index 3c15e551419f..e2b4804695f3 100644 > --- a/drivers/clk/qcom/camcc-sc7180.c > +++ b/drivers/clk/qcom/camcc-sc7180.c > @@ -126,7 +126,9 @@ static struct clk_fixed_factor cam_cc_pll2_out_early = { > .div = 2, > .hw.init = &(struct clk_init_data){ > .name = "cam_cc_pll2_out_early", > - .parent_names = (const char *[]){ "cam_cc_pll2" }, > + .parent_hws = (const struct clk_hw*[]){ > + &cam_cc_pll2.clkr.hw, > + }, > .num_parents = 1, > .ops = &clk_fixed_factor_ops, > }, > @@ -146,8 +148,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll2_out_aux = { > .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_AGERA], > .clkr.hw.init = &(struct clk_init_data){ > .name = "cam_cc_pll2_out_aux", > - .parent_data = &(const struct clk_parent_data){ > - .hw = &cam_cc_pll2.clkr.hw, > + .parent_hws = (const struct clk_hw*[]){ > + &cam_cc_pll2.clkr.hw, > }, > .num_parents = 1, > .flags = CLK_SET_RATE_PARENT, > @@ -729,8 +731,8 @@ static struct clk_branch cam_cc_bps_ahb_clk = { > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "cam_cc_bps_ahb_clk", > - .parent_data = &(const struct clk_parent_data){ > - .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, > + .parent_hws = (const struct clk_hw*[]){ > + &cam_cc_slow_ahb_clk_src.clkr.hw, > }, > .num_parents = 1, > .flags = CLK_SET_RATE_PARENT, > @@ -747,8 +749,8 @@ static struct clk_branch cam_cc_bps_areg_clk = { > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "cam_cc_bps_areg_clk", > - .parent_data = &(const struct clk_parent_data){ > - .hw = &cam_cc_fast_ahb_clk_src.clkr.hw, > + .parent_hws = (const struct clk_hw*[]){ > + &cam_cc_fast_ahb_clk_src.clkr.hw, > }, > .num_parents = 1, > .flags = CLK_SET_RATE_PARENT, > @@ -778,8 +780,8 @@ static struct clk_branch cam_cc_bps_clk = { > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "cam_cc_bps_clk", > - .parent_data = &(const struct clk_parent_data){ > - .hw = &cam_cc_bps_clk_src.clkr.hw, > + .parent_hws = (const struct clk_hw*[]){ > + &cam_cc_bps_clk_src.clkr.hw, > }, > .num_parents = 1, > .flags = CLK_SET_RATE_PARENT, > @@ -809,8 +811,8 @@ static struct clk_branch cam_cc_cci_0_clk = { > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "cam_cc_cci_0_clk", > - .parent_data = &(const struct clk_parent_data){ > - .hw = &cam_cc_cci_0_clk_src.clkr.hw, > + .parent_hws = (const struct clk_hw*[]){ > + &cam_cc_cci_0_clk_src.clkr.hw, > }, > .num_parents = 1, > .flags = CLK_SET_RATE_PARENT, > @@ -827,8 +829,8 @@ static struct clk_branch cam_cc_cci_1_clk = { > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "cam_cc_cci_1_clk", > - .parent_data = &(const struct clk_parent_data){ > - .hw = &cam_cc_cci_1_clk_src.clkr.hw, > + .parent_hws = (const struct clk_hw*[]){ > + &cam_cc_cci_1_clk_src.clkr.hw, > }, > .num_parents = 1, > .flags = CLK_SET_RATE_PARENT, > @@ -845,8 +847,8 @@ static struct clk_branch cam_cc_core_ahb_clk = { > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "cam_cc_core_ahb_clk", > - .parent_data = &(const struct clk_parent_data){ > - .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, > + .parent_hws = (const struct clk_hw*[]){ > + &cam_cc_slow_ahb_clk_src.clkr.hw, > }, > .num_parents = 1, > .flags = CLK_SET_RATE_PARENT, > @@ -863,8 +865,8 @@ static struct clk_branch cam_cc_cpas_ahb_clk = { > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "cam_cc_cpas_ahb_clk", > - .parent_data = &(const struct clk_parent_data){ > - .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, > + .parent_hws = (const struct clk_hw*[]){ > + &cam_cc_slow_ahb_clk_src.clkr.hw, > }, > .num_parents = 1, > .flags = CLK_SET_RATE_PARENT, > @@ -881,8 +883,8 @@ static struct clk_branch cam_cc_csi0phytimer_clk = { > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "cam_cc_csi0phytimer_clk", > - .parent_data = &(const struct clk_parent_data){ > - .hw = &cam_cc_csi0phytimer_clk_src.clkr.hw, > + .parent_hws = (const struct clk_hw*[]){ > + &cam_cc_csi0phytimer_clk_src.clkr.hw, > }, > .num_parents = 1, > .flags = CLK_SET_RATE_PARENT, > @@ -899,8 +901,8 @@ static struct clk_branch cam_cc_csi1phytimer_clk = { > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "cam_cc_csi1phytimer_clk", > - .parent_data = &(const struct clk_parent_data){ > - .hw = &cam_cc_csi1phytimer_clk_src.clkr.hw, > + .parent_hws = (const struct clk_hw*[]){ > + &cam_cc_csi1phytimer_clk_src.clkr.hw, > }, > .num_parents = 1, > .flags = CLK_SET_RATE_PARENT, > @@ -917,8 +919,8 @@ static struct clk_branch cam_cc_csi2phytimer_clk = { > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "cam_cc_csi2phytimer_clk", > - .parent_data = &(const struct clk_parent_data){ > - .hw = &cam_cc_csi2phytimer_clk_src.clkr.hw, > + .parent_hws = (const struct clk_hw*[]){ > + &cam_cc_csi2phytimer_clk_src.clkr.hw, > }, > .num_parents = 1, > .flags = CLK_SET_RATE_PARENT, > @@ -935,8 +937,8 @@ static struct clk_branch cam_cc_csi3phytimer_clk = { > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "cam_cc_csi3phytimer_clk", > - .parent_data = &(const struct clk_parent_data){ > - .hw = &cam_cc_csi3phytimer_clk_src.clkr.hw, > + .parent_hws = (const struct clk_hw*[]){ > + &cam_cc_csi3phytimer_clk_src.clkr.hw, > }, > .num_parents = 1, > .flags = CLK_SET_RATE_PARENT, > @@ -953,8 +955,8 @@ static struct clk_branch cam_cc_csiphy0_clk = { > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "cam_cc_csiphy0_clk", > - .parent_data = &(const struct clk_parent_data){ > - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, > + .parent_hws = (const struct clk_hw*[]){ > + &cam_cc_cphy_rx_clk_src.clkr.hw, > }, > .num_parents = 1, > .flags = CLK_SET_RATE_PARENT, > @@ -971,8 +973,8 @@ static struct clk_branch cam_cc_csiphy1_clk = { > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "cam_cc_csiphy1_clk", > - .parent_data = &(const struct clk_parent_data){ > - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, > + .parent_hws = (const struct clk_hw*[]){ > + &cam_cc_cphy_rx_clk_src.clkr.hw, > }, > .num_parents = 1, > .flags = CLK_SET_RATE_PARENT, > @@ -989,8 +991,8 @@ static struct clk_branch cam_cc_csiphy2_clk = { > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "cam_cc_csiphy2_clk", > - .parent_data = &(const struct clk_parent_data){ > - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, > + .parent_hws = (const struct clk_hw*[]){ > + &cam_cc_cphy_rx_clk_src.clkr.hw, > }, > .num_parents = 1, > .flags = CLK_SET_RATE_PARENT, > @@ -1007,8 +1009,8 @@ static struct clk_branch cam_cc_csiphy3_clk = { > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "cam_cc_csiphy3_clk", > - .parent_data = &(const struct clk_parent_data){ > - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, > + .parent_hws = (const struct clk_hw*[]){ > + &cam_cc_cphy_rx_clk_src.clkr.hw, > }, > .num_parents = 1, > .flags = CLK_SET_RATE_PARENT, > @@ -1025,8 +1027,8 @@ static struct clk_branch cam_cc_icp_clk = { > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "cam_cc_icp_clk", > - .parent_data = &(const struct clk_parent_data){ > - .hw = &cam_cc_icp_clk_src.clkr.hw, > + .parent_hws = (const struct clk_hw*[]){ > + &cam_cc_icp_clk_src.clkr.hw, > }, > .num_parents = 1, > .flags = CLK_SET_RATE_PARENT, > @@ -1056,8 +1058,8 @@ static struct clk_branch cam_cc_ife_0_clk = { > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "cam_cc_ife_0_clk", > - .parent_data = &(const struct clk_parent_data){ > - .hw = &cam_cc_ife_0_clk_src.clkr.hw, > + .parent_hws = (const struct clk_hw*[]){ > + &cam_cc_ife_0_clk_src.clkr.hw, > }, > .num_parents = 1, > .flags = CLK_SET_RATE_PARENT, > @@ -1074,8 +1076,8 @@ static struct clk_branch cam_cc_ife_0_cphy_rx_clk = { > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "cam_cc_ife_0_cphy_rx_clk", > - .parent_data = &(const struct clk_parent_data){ > - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, > + .parent_hws = (const struct clk_hw*[]){ > + &cam_cc_cphy_rx_clk_src.clkr.hw, > }, > .num_parents = 1, > .flags = CLK_SET_RATE_PARENT, > @@ -1092,8 +1094,8 @@ static struct clk_branch cam_cc_ife_0_csid_clk = { > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "cam_cc_ife_0_csid_clk", > - .parent_data = &(const struct clk_parent_data){ > - .hw = &cam_cc_ife_0_csid_clk_src.clkr.hw, > + .parent_hws = (const struct clk_hw*[]){ > + &cam_cc_ife_0_csid_clk_src.clkr.hw, > }, > .num_parents = 1, > .flags = CLK_SET_RATE_PARENT, > @@ -1110,8 +1112,8 @@ static struct clk_branch cam_cc_ife_0_dsp_clk = { > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "cam_cc_ife_0_dsp_clk", > - .parent_data = &(const struct clk_parent_data){ > - .hw = &cam_cc_ife_0_clk_src.clkr.hw, > + .parent_hws = (const struct clk_hw*[]){ > + &cam_cc_ife_0_clk_src.clkr.hw, > }, > .num_parents = 1, > .flags = CLK_SET_RATE_PARENT, > @@ -1141,8 +1143,8 @@ static struct clk_branch cam_cc_ife_1_clk = { > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "cam_cc_ife_1_clk", > - .parent_data = &(const struct clk_parent_data){ > - .hw = &cam_cc_ife_1_clk_src.clkr.hw, > + .parent_hws = (const struct clk_hw*[]){ > + &cam_cc_ife_1_clk_src.clkr.hw, > }, > .num_parents = 1, > .flags = CLK_SET_RATE_PARENT, > @@ -1159,8 +1161,8 @@ static struct clk_branch cam_cc_ife_1_cphy_rx_clk = { > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "cam_cc_ife_1_cphy_rx_clk", > - .parent_data = &(const struct clk_parent_data){ > - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, > + .parent_hws = (const struct clk_hw*[]){ > + &cam_cc_cphy_rx_clk_src.clkr.hw, > }, > .num_parents = 1, > .flags = CLK_SET_RATE_PARENT, > @@ -1177,8 +1179,8 @@ static struct clk_branch cam_cc_ife_1_csid_clk = { > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "cam_cc_ife_1_csid_clk", > - .parent_data = &(const struct clk_parent_data){ > - .hw = &cam_cc_ife_1_csid_clk_src.clkr.hw, > + .parent_hws = (const struct clk_hw*[]){ > + &cam_cc_ife_1_csid_clk_src.clkr.hw, > }, > .num_parents = 1, > .flags = CLK_SET_RATE_PARENT, > @@ -1195,8 +1197,8 @@ static struct clk_branch cam_cc_ife_1_dsp_clk = { > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "cam_cc_ife_1_dsp_clk", > - .parent_data = &(const struct clk_parent_data){ > - .hw = &cam_cc_ife_1_clk_src.clkr.hw, > + .parent_hws = (const struct clk_hw*[]){ > + &cam_cc_ife_1_clk_src.clkr.hw, > }, > .num_parents = 1, > .flags = CLK_SET_RATE_PARENT, > @@ -1213,8 +1215,8 @@ static struct clk_branch cam_cc_ife_lite_clk = { > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "cam_cc_ife_lite_clk", > - .parent_data = &(const struct clk_parent_data){ > - .hw = &cam_cc_ife_lite_clk_src.clkr.hw, > + .parent_hws = (const struct clk_hw*[]){ > + &cam_cc_ife_lite_clk_src.clkr.hw, > }, > .num_parents = 1, > .flags = CLK_SET_RATE_PARENT, > @@ -1231,8 +1233,8 @@ static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "cam_cc_ife_lite_cphy_rx_clk", > - .parent_data = &(const struct clk_parent_data){ > - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, > + .parent_hws = (const struct clk_hw*[]){ > + &cam_cc_cphy_rx_clk_src.clkr.hw, > }, > .num_parents = 1, > .flags = CLK_SET_RATE_PARENT, > @@ -1249,8 +1251,8 @@ static struct clk_branch cam_cc_ife_lite_csid_clk = { > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "cam_cc_ife_lite_csid_clk", > - .parent_data = &(const struct clk_parent_data){ > - .hw = &cam_cc_ife_lite_csid_clk_src.clkr.hw, > + .parent_hws = (const struct clk_hw*[]){ > + &cam_cc_ife_lite_csid_clk_src.clkr.hw, > }, > .num_parents = 1, > .flags = CLK_SET_RATE_PARENT, > @@ -1267,8 +1269,8 @@ static struct clk_branch cam_cc_ipe_0_ahb_clk = { > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "cam_cc_ipe_0_ahb_clk", > - .parent_data = &(const struct clk_parent_data){ > - .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, > + .parent_hws = (const struct clk_hw*[]){ > + &cam_cc_slow_ahb_clk_src.clkr.hw, > }, > .num_parents = 1, > .flags = CLK_SET_RATE_PARENT, > @@ -1285,8 +1287,8 @@ static struct clk_branch cam_cc_ipe_0_areg_clk = { > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "cam_cc_ipe_0_areg_clk", > - .parent_data = &(const struct clk_parent_data){ > - .hw = &cam_cc_fast_ahb_clk_src.clkr.hw, > + .parent_hws = (const struct clk_hw*[]){ > + &cam_cc_fast_ahb_clk_src.clkr.hw, > }, > .num_parents = 1, > .flags = CLK_SET_RATE_PARENT, > @@ -1316,8 +1318,8 @@ static struct clk_branch cam_cc_ipe_0_clk = { > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "cam_cc_ipe_0_clk", > - .parent_data = &(const struct clk_parent_data){ > - .hw = &cam_cc_ipe_0_clk_src.clkr.hw, > + .parent_hws = (const struct clk_hw*[]){ > + &cam_cc_ipe_0_clk_src.clkr.hw, > }, > .num_parents = 1, > .flags = CLK_SET_RATE_PARENT, > @@ -1334,8 +1336,8 @@ static struct clk_branch cam_cc_jpeg_clk = { > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "cam_cc_jpeg_clk", > - .parent_data = &(const struct clk_parent_data){ > - .hw = &cam_cc_jpeg_clk_src.clkr.hw, > + .parent_hws = (const struct clk_hw*[]){ > + &cam_cc_jpeg_clk_src.clkr.hw, > }, > .num_parents = 1, > .flags = CLK_SET_RATE_PARENT, > @@ -1352,8 +1354,8 @@ static struct clk_branch cam_cc_lrme_clk = { > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "cam_cc_lrme_clk", > - .parent_data = &(const struct clk_parent_data){ > - .hw = &cam_cc_lrme_clk_src.clkr.hw, > + .parent_hws = (const struct clk_hw*[]){ > + &cam_cc_lrme_clk_src.clkr.hw, > }, > .num_parents = 1, > .flags = CLK_SET_RATE_PARENT, > @@ -1370,8 +1372,8 @@ static struct clk_branch cam_cc_mclk0_clk = { > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "cam_cc_mclk0_clk", > - .parent_data = &(const struct clk_parent_data){ > - .hw = &cam_cc_mclk0_clk_src.clkr.hw, > + .parent_hws = (const struct clk_hw*[]){ > + &cam_cc_mclk0_clk_src.clkr.hw, > }, > .num_parents = 1, > .flags = CLK_SET_RATE_PARENT, > @@ -1388,8 +1390,8 @@ static struct clk_branch cam_cc_mclk1_clk = { > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "cam_cc_mclk1_clk", > - .parent_data = &(const struct clk_parent_data){ > - .hw = &cam_cc_mclk1_clk_src.clkr.hw, > + .parent_hws = (const struct clk_hw*[]){ > + &cam_cc_mclk1_clk_src.clkr.hw, > }, > .num_parents = 1, > .flags = CLK_SET_RATE_PARENT, > @@ -1406,8 +1408,8 @@ static struct clk_branch cam_cc_mclk2_clk = { > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "cam_cc_mclk2_clk", > - .parent_data = &(const struct clk_parent_data){ > - .hw = &cam_cc_mclk2_clk_src.clkr.hw, > + .parent_hws = (const struct clk_hw*[]){ > + &cam_cc_mclk2_clk_src.clkr.hw, > }, > .num_parents = 1, > .flags = CLK_SET_RATE_PARENT, > @@ -1424,8 +1426,8 @@ static struct clk_branch cam_cc_mclk3_clk = { > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "cam_cc_mclk3_clk", > - .parent_data = &(const struct clk_parent_data){ > - .hw = &cam_cc_mclk3_clk_src.clkr.hw, > + .parent_hws = (const struct clk_hw*[]){ > + &cam_cc_mclk3_clk_src.clkr.hw, > }, > .num_parents = 1, > .flags = CLK_SET_RATE_PARENT, > @@ -1442,8 +1444,8 @@ static struct clk_branch cam_cc_mclk4_clk = { > .enable_mask = BIT(0), > .hw.init = &(struct clk_init_data){ > .name = "cam_cc_mclk4_clk", > - .parent_data = &(const struct clk_parent_data){ > - .hw = &cam_cc_mclk4_clk_src.clkr.hw, > + .parent_hws = (const struct clk_hw*[]){ > + &cam_cc_mclk4_clk_src.clkr.hw, > }, > .num_parents = 1, > .flags = CLK_SET_RATE_PARENT, > -- > 2.33.0 >
Quoting Dmitry Baryshkov (2021-12-08 09:54:25) > If all parents are specified as clk_hw, we can use parent_hws instead of > parent_data. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- Is the code size smaller? Would be nice to add that detail. Reviewed-by: Stephen Boyd <sboyd@kernel.org>
On 09/12/2021 11:11, Stephen Boyd wrote: > Quoting Dmitry Baryshkov (2021-12-08 09:54:25) >> If all parents are specified as clk_hw, we can use parent_hws instead of >> parent_data. >> >> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >> --- > > Is the code size smaller? Would be nice to add that detail. The bloat-o-meter reports zero size difference. > Reviewed-by: Stephen Boyd <sboyd@kernel.org>
diff --git a/drivers/clk/qcom/camcc-sc7180.c b/drivers/clk/qcom/camcc-sc7180.c index 3c15e551419f..e2b4804695f3 100644 --- a/drivers/clk/qcom/camcc-sc7180.c +++ b/drivers/clk/qcom/camcc-sc7180.c @@ -126,7 +126,9 @@ static struct clk_fixed_factor cam_cc_pll2_out_early = { .div = 2, .hw.init = &(struct clk_init_data){ .name = "cam_cc_pll2_out_early", - .parent_names = (const char *[]){ "cam_cc_pll2" }, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_pll2.clkr.hw, + }, .num_parents = 1, .ops = &clk_fixed_factor_ops, }, @@ -146,8 +148,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll2_out_aux = { .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_AGERA], .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_pll2_out_aux", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_pll2.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_pll2.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -729,8 +731,8 @@ static struct clk_branch cam_cc_bps_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_bps_ahb_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_slow_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -747,8 +749,8 @@ static struct clk_branch cam_cc_bps_areg_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_bps_areg_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_fast_ahb_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_fast_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -778,8 +780,8 @@ static struct clk_branch cam_cc_bps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_bps_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_bps_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_bps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -809,8 +811,8 @@ static struct clk_branch cam_cc_cci_0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_cci_0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_cci_0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cci_0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -827,8 +829,8 @@ static struct clk_branch cam_cc_cci_1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_cci_1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_cci_1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cci_1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -845,8 +847,8 @@ static struct clk_branch cam_cc_core_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_core_ahb_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_slow_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -863,8 +865,8 @@ static struct clk_branch cam_cc_cpas_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_cpas_ahb_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_slow_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -881,8 +883,8 @@ static struct clk_branch cam_cc_csi0phytimer_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csi0phytimer_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_csi0phytimer_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_csi0phytimer_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -899,8 +901,8 @@ static struct clk_branch cam_cc_csi1phytimer_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csi1phytimer_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_csi1phytimer_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_csi1phytimer_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -917,8 +919,8 @@ static struct clk_branch cam_cc_csi2phytimer_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csi2phytimer_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_csi2phytimer_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_csi2phytimer_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -935,8 +937,8 @@ static struct clk_branch cam_cc_csi3phytimer_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csi3phytimer_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_csi3phytimer_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_csi3phytimer_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -953,8 +955,8 @@ static struct clk_branch cam_cc_csiphy0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csiphy0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -971,8 +973,8 @@ static struct clk_branch cam_cc_csiphy1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csiphy1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -989,8 +991,8 @@ static struct clk_branch cam_cc_csiphy2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csiphy2_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1007,8 +1009,8 @@ static struct clk_branch cam_cc_csiphy3_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csiphy3_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1025,8 +1027,8 @@ static struct clk_branch cam_cc_icp_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_icp_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_icp_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_icp_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1056,8 +1058,8 @@ static struct clk_branch cam_cc_ife_0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_ife_0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1074,8 +1076,8 @@ static struct clk_branch cam_cc_ife_0_cphy_rx_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_cphy_rx_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1092,8 +1094,8 @@ static struct clk_branch cam_cc_ife_0_csid_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_csid_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_ife_0_csid_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_0_csid_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1110,8 +1112,8 @@ static struct clk_branch cam_cc_ife_0_dsp_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_dsp_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_ife_0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1141,8 +1143,8 @@ static struct clk_branch cam_cc_ife_1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_ife_1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1159,8 +1161,8 @@ static struct clk_branch cam_cc_ife_1_cphy_rx_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_cphy_rx_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1177,8 +1179,8 @@ static struct clk_branch cam_cc_ife_1_csid_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_csid_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_ife_1_csid_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_1_csid_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1195,8 +1197,8 @@ static struct clk_branch cam_cc_ife_1_dsp_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_dsp_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_ife_1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1213,8 +1215,8 @@ static struct clk_branch cam_cc_ife_lite_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_ife_lite_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_lite_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1231,8 +1233,8 @@ static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_cphy_rx_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1249,8 +1251,8 @@ static struct clk_branch cam_cc_ife_lite_csid_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_csid_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_ife_lite_csid_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_lite_csid_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1267,8 +1269,8 @@ static struct clk_branch cam_cc_ipe_0_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_0_ahb_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_slow_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1285,8 +1287,8 @@ static struct clk_branch cam_cc_ipe_0_areg_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_0_areg_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_fast_ahb_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_fast_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1316,8 +1318,8 @@ static struct clk_branch cam_cc_ipe_0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_ipe_0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ipe_0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1334,8 +1336,8 @@ static struct clk_branch cam_cc_jpeg_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_jpeg_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_jpeg_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_jpeg_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1352,8 +1354,8 @@ static struct clk_branch cam_cc_lrme_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_lrme_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_lrme_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_lrme_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1370,8 +1372,8 @@ static struct clk_branch cam_cc_mclk0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_mclk0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_mclk0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1388,8 +1390,8 @@ static struct clk_branch cam_cc_mclk1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_mclk1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_mclk1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1406,8 +1408,8 @@ static struct clk_branch cam_cc_mclk2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk2_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_mclk2_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_mclk2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1424,8 +1426,8 @@ static struct clk_branch cam_cc_mclk3_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk3_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_mclk3_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_mclk3_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1442,8 +1444,8 @@ static struct clk_branch cam_cc_mclk4_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk4_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_mclk4_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_mclk4_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT,
If all parents are specified as clk_hw, we can use parent_hws instead of parent_data. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/camcc-sc7180.c | 156 ++++++++++++++++---------------- 1 file changed, 79 insertions(+), 77 deletions(-)