| Message ID | 20220117104016.23046-1-slark_xiao@163.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | [net] bus: mhi: Add mru_default for Foxconn SDX55 and Cinterion MV31-W | expand |
diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 3a258a677df8..b79895810c52 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -366,6 +366,7 @@ static const struct mhi_pci_dev_info mhi_foxconn_sdx55_info = { .config = &modem_foxconn_sdx55_config, .bar_num = MHI_PCI_DEFAULT_BAR_NUM, .dma_data_width = 32, + .mru_default = 32768, .sideband_wake = false, }; @@ -401,6 +402,7 @@ static const struct mhi_pci_dev_info mhi_mv31_info = { .config = &modem_mv31_config, .bar_num = MHI_PCI_DEFAULT_BAR_NUM, .dma_data_width = 32, + .mru_default = 32768, }; static const struct mhi_channel_config mhi_sierra_em919x_channels[] = {
For default mechanism, product would use default MRU 3500 if they didn't define it. But for Foxconn SDX55, there is a known issue which MRU 3500 would lead to data connection lost. So we align it with Qualcomm default MRU settings. We also validate it with Cinterion product and find it also works. Fixes: aac426562f56 ("bus: mhi: pci_generic: Introduce Foxconn T99W175 support") Fixes: 87693e092bd0 ("bus: mhi: pci_generic: Add Cinterion MV31-W PCIe to MHI") Signed-off-by: Slark Xiao <slark_xiao@163.com> --- drivers/bus/mhi/pci_generic.c | 2 ++ 1 file changed, 2 insertions(+)