From patchwork Wed Feb 23 19:29:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 12757450 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CFAB6C433FE for ; Wed, 23 Feb 2022 19:30:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237525AbiBWTax (ORCPT ); Wed, 23 Feb 2022 14:30:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48410 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244408AbiBWTaw (ORCPT ); Wed, 23 Feb 2022 14:30:52 -0500 Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9281A4832A for ; Wed, 23 Feb 2022 11:30:22 -0800 (PST) Received: by mail-pj1-x102e.google.com with SMTP id m13-20020a17090aab0d00b001bbe267d4d1so4253584pjq.0 for ; Wed, 23 Feb 2022 11:30:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yYf0qM8EzXfF4UkYBAdwkh5DAfiu0yUybShsdnlJ+V0=; b=xpLVibRZlPiuJ+Toe8/fPJzR6Jht5ma1bxsj8Dy3MGK7eigeI8UmN26mRiOFs/Gz3c ZxXUFzGCZi6Jj898rCXfgDyRWxIHmA8URMjY5hxs4czB9wAJlvQ/UA98d9r13fpY2YtW dhjMHP6XHhdwrHgydlBEoThZV08JZEFgp2rUmpNByxZbyqFMFXdRr/JBVcpHSanN7zko gUgjDNOutKuJovJn5GMi+YycGwMEDs7BdIlPR26JMW2TvOCW54azJh0gATZKi7ZUFxLM 59JZpcDuMyhK+RLxQCr2JPkOTbBnZydZFmHTa0rmTDsTuwLu6EOBL/3OXsfUxsGylNwF PHSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yYf0qM8EzXfF4UkYBAdwkh5DAfiu0yUybShsdnlJ+V0=; b=XqTugMOpbELkGMuNabWDPI8XLOuyBIbNgRUPHgRJCQYosCGmWYKyDpEq2gM0jnv+O/ XrsJIEq3lgYAsiuixvBtEc0b6tRt3Kg13tKF1xuHiuV7kfnvmzRntdQ7wS1i2409kOQn aOIlJmAD39QRsAdzkildJJOIa4eclnHCRNSVNtuqWLSpYvKVaaz0Gjmd6gd1w1foN+Tj EaRc+HiMtuEwIva9zDRSPo5d2B88wa0ACPBNSzPSLkFI0KnU9MxWr4TXTau/lo/Qn9ZL VPMWQoFJ0aa7xUK8e330kbizMrNfHt2eCZHu72vdGGGtsF5izIye8x70rNkwKTZ+ETqF 1zNg== X-Gm-Message-State: AOAM533zREfgIKiueEFzhEBnmdJqR9P785mDu9YmGzE3iMBZhKrZ+KU7 MB9nK0+sid5+faVHf1iVwPcxxdQUdV1J/A== X-Google-Smtp-Source: ABdhPJzhVl8/iwqfz4h0Jx2H9qID7UYMgoGd25UBO/+SkRGcd0r67FxMbxy8bMCtMxXNvCcur7P2fA== X-Received: by 2002:a17:903:192:b0:14f:ff7c:33db with SMTP id z18-20020a170903019200b0014fff7c33dbmr1240344plg.75.1645644621859; Wed, 23 Feb 2022 11:30:21 -0800 (PST) Received: from localhost.localdomain ([2402:3a80:180f:6b3c:fda0:57e9:7d44:2aa7]) by smtp.gmail.com with ESMTPSA id z10-20020a17090a8b8a00b001b8d20074c8sm3719917pjn.33.2022.02.23.11.30.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Feb 2022 11:30:21 -0800 (PST) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org Cc: bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, lorenzo.pieralisi@arm.com, agross@kernel.org, bjorn.andersson@linaro.org, svarbanov@mm-sol.com, bhelgaas@google.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, Vinod Koul Subject: [PATCH 3/6] phy: qcom-qmp: Add SM8150 PCIe QMP PHYs Date: Thu, 24 Feb 2022 00:59:43 +0530 Message-Id: <20220223192946.473172-4-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220223192946.473172-1-bhupesh.sharma@linaro.org> References: <20220223192946.473172-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org SM8150 has multiple (different) PHY versions: QMP GEN3x1 PHY - 1 lane QMP GEN3x2 PHY - 2 lanes Add support for these with relevant init sequence. Cc: Bjorn Andersson Cc: Vinod Koul Signed-off-by: Bhupesh Sharma --- drivers/phy/qualcomm/phy-qcom-qmp.c | 90 +++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index 8ea87c69f463..0805c1bab690 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -3294,6 +3294,11 @@ static const char * const sdm845_pciephy_clk_l[] = { "aux", "cfg_ahb", "ref", "refgen", }; +/* the pcie phy on sm8150 doesn't have a ref clock */ +static const char * const sm8150_pciephy_clk_l[] = { + "aux", "cfg_ahb", "refgen", +}; + static const char * const qmp_v4_phy_clk_l[] = { "aux", "ref_clk_src", "ref", "com_aux", }; @@ -3583,6 +3588,85 @@ static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { .pwrdn_delay_max = 1005, /* us */ }; +static const struct qmp_phy_cfg sm8150_qmp_gen3x1_pciephy_cfg = { + .type = PHY_TYPE_PCIE, + .nlanes = 1, + + .serdes_tbl = sm8250_qmp_pcie_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), + .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl, + .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl), + .tx_tbl = sm8250_qmp_pcie_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), + .rx_tbl = sm8250_qmp_pcie_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), + .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl, + .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl), + .pcs_tbl = sm8250_qmp_pcie_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), + .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl, + .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl), + .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl, + .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), + .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, + .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), + .clk_list = sm8150_pciephy_clk_l, + .num_clks = ARRAY_SIZE(sm8150_pciephy_clk_l), + .reset_list = sdm845_pciephy_reset_l, + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = sm8250_pcie_regs_layout, + + .start_ctrl = PCS_START | SERDES_START, + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS, + + .has_pwrdn_delay = true, + .pwrdn_delay_min = 995, /* us */ + .pwrdn_delay_max = 1005, /* us */ +}; + +static const struct qmp_phy_cfg sm8150_qmp_gen3x2_pciephy_cfg = { + .type = PHY_TYPE_PCIE, + .nlanes = 2, + + .serdes_tbl = sm8250_qmp_pcie_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), + .tx_tbl = sm8250_qmp_pcie_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), + .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl, + .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl), + .rx_tbl = sm8250_qmp_pcie_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), + .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl, + .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl), + .pcs_tbl = sm8250_qmp_pcie_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), + .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl, + .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl), + .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl, + .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), + .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, + .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), + .clk_list = sm8150_pciephy_clk_l, + .num_clks = ARRAY_SIZE(sm8150_pciephy_clk_l), + .reset_list = sdm845_pciephy_reset_l, + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = sm8250_pcie_regs_layout, + + .start_ctrl = PCS_START | SERDES_START, + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS, + + .is_dual_lane_phy = true, + .has_pwrdn_delay = true, + .pwrdn_delay_min = 995, /* us */ + .pwrdn_delay_max = 1005, /* us */ +}; + static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { .type = PHY_TYPE_PCIE, .nlanes = 1, @@ -6004,6 +6088,12 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = { }, { .compatible = "qcom,sm6115-qmp-ufs-phy", .data = &sm6115_ufsphy_cfg, + }, { + .compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy", + .data = &sm8150_qmp_gen3x1_pciephy_cfg, + }, { + .compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy", + .data = &sm8150_qmp_gen3x2_pciephy_cfg, }, { .compatible = "qcom,sm8150-qmp-ufs-phy", .data = &sm8150_ufsphy_cfg,