From patchwork Mon Mar 14 11:42:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Zapolskiy X-Patchwork-Id: 12780067 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2776C3527D for ; Mon, 14 Mar 2022 11:43:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239553AbiCNLpE (ORCPT ); Mon, 14 Mar 2022 07:45:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43966 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240518AbiCNLoE (ORCPT ); Mon, 14 Mar 2022 07:44:04 -0400 Received: from mail-lj1-x22d.google.com (mail-lj1-x22d.google.com [IPv6:2a00:1450:4864:20::22d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E61EBC38 for ; Mon, 14 Mar 2022 04:42:53 -0700 (PDT) Received: by mail-lj1-x22d.google.com with SMTP id r22so21428439ljd.4 for ; Mon, 14 Mar 2022 04:42:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OBnwU3nqmmc0u3iNZ0+MBmfjgblQfRJpOZDSvEQruOg=; b=sEJe5AnawknBUfXVBLfzA3KY8zaxhbFebIBPNUuVAuS7XUjGjL/SB/EXT0G2vdxckk JLHxBGGnQQX8kxH07erWZsoh2RuIfrHgwjts+8GvtfeqR8RvmQlLn6Yq1Hv1aycu1BNy 6LQXow6SOiW18UweHIRJE8D2aukXC8dUMHK4bE70nLXo0JwhizybSwZbkUEOusnBKg2z aj8BSNfLW0WYrBQ+Hgvk7GZJOQr9V35+hX1lVKTdQTrc9jhSRr3YKcOA/7AqNWnzyzPs Mg5nQzjzJWecppDAWHkEOnpjldniKNB5MqI7lyrm5/+Wk5Wh/tR9L2XhPbkPjm6hqwOP hiNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OBnwU3nqmmc0u3iNZ0+MBmfjgblQfRJpOZDSvEQruOg=; b=mg0GQFcPOt+uNReT/NEJsLkvhKafhcXebLIkvTu3EFzn5slhWpTnbOg0/8oke/8CrI hqYJnn43LHyDKYALpq+k4+/st8H4SUsf6+ufG1FnfaratDQJFZD/fHOaUOACAQgcYV5z G9ZUrycycGsMvZ0BW/MLAjqT8/nVb5cW98QUxt1N3feVd/5IkoFzVeaRhYan1nNrywZz lFkcK//Vvok76n83XlFuEQJZ1fVs3mLxL5N2ytUVi1ZWxVbo2qLghg8Frl0KhrsBffai MOtj51EXl6KMfIe1lrRyg5WXAyQHZsvdoIhTL2ssV+KgUf9/8JCd5LumIYuXt4QpzdkW yYEQ== X-Gm-Message-State: AOAM532476F1P7u7dQhYZ6SvfrY1BhRmv7yah6EH8OTPFuzLRgnRaI7s mcIHrsGxW6SL41vmBMLBTD10vg== X-Google-Smtp-Source: ABdhPJxugzsFKWcXstfl3sTjDapzkQ3DoVRok6ymNeCOaZNyAVvHlaxJAp0BO1yy3Z1y8hGNpouM5w== X-Received: by 2002:a2e:bc0e:0:b0:247:f348:d6dd with SMTP id b14-20020a2ebc0e000000b00247f348d6ddmr14172154ljf.323.1647258172288; Mon, 14 Mar 2022 04:42:52 -0700 (PDT) Received: from localhost.localdomain (88-113-46-102.elisa-laajakaista.fi. [88.113.46.102]) by smtp.gmail.com with ESMTPSA id i1-20020a2e8641000000b00247d94a6ac5sm3931690ljj.2.2022.03.14.04.42.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Mar 2022 04:42:52 -0700 (PDT) From: Vladimir Zapolskiy To: Bjorn Andersson Cc: Andy Gross , Stephen Boyd , Michael Turquette , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 6/7] clk: qcom: clk-alpha-pll: add rivian evo PLL configuration interfaces Date: Mon, 14 Mar 2022 13:42:51 +0200 Message-Id: <20220314114251.1636662-1-vladimir.zapolskiy@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220314114211.1636574-1-vladimir.zapolskiy@linaro.org> References: <20220314114211.1636574-1-vladimir.zapolskiy@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The change adds and exports rivian evo PLL configuration and control functions to clock controller drivers. Signed-off-by: Vladimir Zapolskiy --- drivers/clk/qcom/clk-alpha-pll.c | 70 ++++++++++++++++++++++++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 6 +++ 2 files changed, 76 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 54bad5277802..ab4f0fc15a48 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -154,6 +154,18 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { [PLL_OFF_TEST_CTL_U] = 0x30, [PLL_OFF_TEST_CTL_U1] = 0x34, }, + [CLK_ALPHA_PLL_TYPE_RIVIAN_EVO] = { + [PLL_OFF_OPMODE] = 0x04, + [PLL_OFF_STATUS] = 0x0c, + [PLL_OFF_L_VAL] = 0x10, + [PLL_OFF_USER_CTL] = 0x14, + [PLL_OFF_USER_CTL_U] = 0x18, + [PLL_OFF_CONFIG_CTL] = 0x1c, + [PLL_OFF_CONFIG_CTL_U] = 0x20, + [PLL_OFF_CONFIG_CTL_U1] = 0x24, + [PLL_OFF_TEST_CTL] = 0x28, + [PLL_OFF_TEST_CTL_U] = 0x2c, + }, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); @@ -2179,3 +2191,61 @@ const struct clk_ops clk_alpha_pll_lucid_evo_ops = { .set_rate = alpha_pll_lucid_5lpe_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops); + +void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, + const struct alpha_pll_config *config) +{ + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); + clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); + clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); + clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); + + regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); + + regmap_update_bits(regmap, PLL_MODE(pll), + PLL_RESET_N | PLL_BYPASSNL | PLL_OUTCTRL, + PLL_RESET_N | PLL_BYPASSNL); +} +EXPORT_SYMBOL_GPL(clk_rivian_evo_pll_configure); + +static unsigned long clk_rivian_evo_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + u32 l; + + regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); + + return parent_rate * l; +} + +static long clk_rivian_evo_pll_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + unsigned long min_freq, max_freq; + u32 l; + u64 a; + + rate = alpha_pll_round_rate(rate, *prate, &l, &a, 0); + if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) + return rate; + + min_freq = pll->vco_table[0].min_freq; + max_freq = pll->vco_table[pll->num_vco - 1].max_freq; + + return clamp(rate, min_freq, max_freq); +} + +const struct clk_ops clk_alpha_pll_rivian_evo_ops = { + .enable = alpha_pll_lucid_5lpe_enable, + .disable = alpha_pll_lucid_5lpe_disable, + .is_enabled = clk_trion_pll_is_enabled, + .recalc_rate = clk_rivian_evo_pll_recalc_rate, + .round_rate = clk_rivian_evo_pll_round_rate, +}; +EXPORT_SYMBOL_GPL(clk_alpha_pll_rivian_evo_ops); diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 0b7a6859ca2c..447efb82fe59 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -18,6 +18,7 @@ enum { CLK_ALPHA_PLL_TYPE_AGERA, CLK_ALPHA_PLL_TYPE_ZONDA, CLK_ALPHA_PLL_TYPE_LUCID_EVO, + CLK_ALPHA_PLL_TYPE_RIVIAN_EVO, CLK_ALPHA_PLL_TYPE_MAX, }; @@ -157,6 +158,9 @@ extern const struct clk_ops clk_alpha_pll_lucid_evo_ops; extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops; extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops; +extern const struct clk_ops clk_alpha_pll_rivian_evo_ops; +#define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_ops + void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config); void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, @@ -172,5 +176,7 @@ void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config); void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config); +void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, + const struct alpha_pll_config *config); #endif