From patchwork Mon Apr 25 04:02:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mao Jinlong X-Patchwork-Id: 12825270 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 857B0C433F5 for ; Mon, 25 Apr 2022 04:04:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240869AbiDYEHC (ORCPT ); Mon, 25 Apr 2022 00:07:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53884 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240890AbiDYEGz (ORCPT ); Mon, 25 Apr 2022 00:06:55 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B600A36B6D; Sun, 24 Apr 2022 21:03:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1650859431; x=1682395431; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=Z/F+QNe/FmpxcYeQ+oVHB2mCeoq+zFP4zW8sLVNDw1Q=; b=QKQ8Bv5ibiQzC4kDvdr1lwVZtb7Y3tCScOC6eO9Izmu9tU40AgwM2000 /D43gI6UjE25eqj5PkUqLovbYMgmRxHmA8Q3z3B90ONDTqcpCF8190OFK 3lyvVhXg5k33Y7NfgKZfQR9hY3SFXS8UdaeluPw7VL/G0z+irJA7U46Gh Y=; Received: from unknown (HELO ironmsg04-sd.qualcomm.com) ([10.53.140.144]) by alexa-out-sd-02.qualcomm.com with ESMTP; 24 Apr 2022 21:03:51 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg04-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2022 21:03:50 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Sun, 24 Apr 2022 21:03:49 -0700 Received: from jinlmao-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Sun, 24 Apr 2022 21:03:45 -0700 From: Mao Jinlong To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin , Konrad Dybcio CC: Mao Jinlong , Mike Leach , Leo Yan , Greg Kroah-Hartman , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Trilok Soni , Hao Zhang , , Bjorn Andersson Subject: [PATCH v6 05/10] coresight-tpdm: Add integration test support Date: Mon, 25 Apr 2022 12:02:59 +0800 Message-ID: <20220425040304.37487-6-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220425040304.37487-1-quic_jinlmao@quicinc.com> References: <20220425040304.37487-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Integration test for tpdm can help to generate the data for verification of the topology during TPDM software bring up. Sample: echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink echo 1 > /sys/bus/coresight/devices/tpdm0/enable_source echo 1 > /sys/bus/coresight/devices/tpdm0/integration_test echo 2 > /sys/bus/coresight/devices/tpdm0/integration_test cat /dev/tmc_etf0 > /data/etf-tpdm0.bin Signed-off-by: Tao Zhang Signed-off-by: Mao Jinlong --- drivers/hwtracing/coresight/coresight-tpdm.c | 54 ++++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 14 +++++ 2 files changed, 68 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 70df888ac565..57e38aa7d2bd 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -123,6 +123,59 @@ static void tpdm_init_default_data(struct tpdm_drvdata *drvdata) CS_LOCK(drvdata->base); } +/* + * value 1: 64 bits test data + * value 2: 32 bits test data + */ +static ssize_t integration_test_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + int i, ret = 0; + unsigned long val; + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + ret = kstrtoul(buf, 10, &val); + if (ret) + return ret; + + if (val != 1 && val != 2) + return -EINVAL; + + if (!drvdata->enable) + return -EINVAL; + + if (val == 1) + val = ATBCNTRL_VAL_64; + else + val = ATBCNTRL_VAL_32; + CS_UNLOCK(drvdata->base); + writel_relaxed(0x1, drvdata->base + TPDM_ITCNTRL); + + for (i = 1; i < INTEGRATION_TEST_CYCLE; i++) + writel_relaxed(val, drvdata->base + TPDM_ITATBCNTRL); + + writel_relaxed(0, drvdata->base + TPDM_ITCNTRL); + CS_LOCK(drvdata->base); + return size; +} +static DEVICE_ATTR_WO(integration_test); + +static struct attribute *tpdm_attrs[] = { + &dev_attr_integration_test.attr, + NULL, +}; + +static struct attribute_group tpdm_attr_grp = { + .attrs = tpdm_attrs, +}; + +static const struct attribute_group *tpdm_attr_grps[] = { + &tpdm_attr_grp, + NULL, +}; + static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) { struct device *dev = &adev->dev; @@ -157,6 +210,7 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) desc.ops = &tpdm_cs_ops; desc.pdata = adev->dev.platform_data; desc.dev = &adev->dev; + desc.groups = tpdm_attr_grps; drvdata->csdev = coresight_register(&desc); if (IS_ERR(drvdata->csdev)) return PTR_ERR(drvdata->csdev); diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index f95aaad9c653..4aa880794383 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -14,6 +14,20 @@ /* Enable bit for DSB subunit */ #define TPDM_DSB_CR_ENA BIT(0) +/* TPDM integration test registers */ +#define TPDM_ITATBCNTRL (0xEF0) +#define TPDM_ITCNTRL (0xF00) + +/* Register value for integration test */ +#define ATBCNTRL_VAL_32 0xC00F1409 +#define ATBCNTRL_VAL_64 0xC01F1409 + +/* + * Number of cycles to write value when + * integration test. + */ +#define INTEGRATION_TEST_CYCLE 10 + /** * This enum is for PERIPHIDR0 register of TPDM. * The fields [6:0] of PERIPHIDR0 are used to determine what