From patchwork Mon May 9 09:01:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Zapolskiy X-Patchwork-Id: 12843209 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 126ADC4167B for ; Mon, 9 May 2022 09:12:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237047AbiEIJQV (ORCPT ); Mon, 9 May 2022 05:16:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36848 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237774AbiEIJGC (ORCPT ); Mon, 9 May 2022 05:06:02 -0400 Received: from mail-lj1-x22d.google.com (mail-lj1-x22d.google.com [IPv6:2a00:1450:4864:20::22d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 86AB21B12FF for ; Mon, 9 May 2022 02:01:58 -0700 (PDT) Received: by mail-lj1-x22d.google.com with SMTP id l19so16173708ljb.7 for ; Mon, 09 May 2022 02:01:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8aGLO+9BnY7wmiY7FHT8CtDrv7XOkUYuM3orNUYouck=; b=kXD9GjLnrFBGqrWPo95Q+fdLAK3GrrPtbwY0OBk7Oljn/ITkrVBIfH95KwJZh12rB3 vxwEGYcM5P408+MKejBmsnzlKWwk3yhgA/jQiEtjgovZQhbTR1bCt+nPK91HLWgfKbV+ QAYOHrkMEqd36xc10zNaDPLQn1U/RumxDIfnPH8YFIqA6H2kXM/dYnzoH8K6aRLUpS01 5lnq/1GdvBMiW4rjAr9wT3crKFKHtg8T275zPG5kQZ9QTcRLUI1R6ALW9j93xX8nUZSE dCvrDzSWfqgAuvn6TAFVAOIxsOP1PJwud5SaBP3BFGe0zwHKb1yA323Dk66/+OYDTQc7 XwdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8aGLO+9BnY7wmiY7FHT8CtDrv7XOkUYuM3orNUYouck=; b=7QzddEezY7n9JYCA2r8QC3lf/7aip+HBX1jQZEUur5Kb3EbpyZaOZm947FvxCzeb1j vnNYUnrNzw62de5phaPRF8s1v2beefghW1yoZcO/6yCfIkNvpXm/sh4qSckEEYZsG4mx u/sYpr43C2GT2lJMr4BimCa0hQMTVHj8ZeDgnYtNrF9I54EzHjz/1pWx6+a3OhMhOabZ +w/sZ0RPUev7+xe4LncKSGGwSyznHcLDoqiTmF10esEkfcdtWAJ6bpFdhQinVJIL7hON Z8fMYZSJuv9Qrk73lKYQMD5WMrzyroTqVujQwu8gr6EK2q4zN1mW/iMsJTV8Xh4tbpVF o7jw== X-Gm-Message-State: AOAM532ANYQSioLRhfjMXiK04ap77zc0NI8jeLkshKDlN1SeyzNCeBEU rZjRy6+KbxKxg5WosYAMSKf42wJ6mRGKgg== X-Google-Smtp-Source: ABdhPJx/+E+xKeFIvfzprzITiTURu46E0pkX2C4b0JFrOKQD2WOVufjvmaZ+ajjNlM+f2WTd/z63IA== X-Received: by 2002:a2e:9583:0:b0:24f:482:e1cd with SMTP id w3-20020a2e9583000000b0024f0482e1cdmr9561413ljh.22.1652086916448; Mon, 09 May 2022 02:01:56 -0700 (PDT) Received: from localhost.localdomain (mobile-access-5672eb-224.dhcp.inet.fi. [86.114.235.224]) by smtp.gmail.com with ESMTPSA id c36-20020a05651223a400b0047255d21132sm1876000lfv.97.2022.05.09.02.01.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 02:01:55 -0700 (PDT) From: Vladimir Zapolskiy To: Bjorn Andersson Cc: Andy Gross , Stephen Boyd , Michael Turquette , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v5 6/7] clk: qcom: clk-alpha-pll: add Rivian EVO PLL configuration interfaces Date: Mon, 9 May 2022 12:01:54 +0300 Message-Id: <20220509090154.4141062-1-vladimir.zapolskiy@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220509090059.4140941-1-vladimir.zapolskiy@linaro.org> References: <20220509090059.4140941-1-vladimir.zapolskiy@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The change adds and exports Rivian EVO PLL configuration and control functions to clock controller drivers. Signed-off-by: Vladimir Zapolskiy --- drivers/clk/qcom/clk-alpha-pll.c | 70 ++++++++++++++++++++++++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 6 +++ 2 files changed, 76 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 54bad5277802..ab4f0fc15a48 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -154,6 +154,18 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { [PLL_OFF_TEST_CTL_U] = 0x30, [PLL_OFF_TEST_CTL_U1] = 0x34, }, + [CLK_ALPHA_PLL_TYPE_RIVIAN_EVO] = { + [PLL_OFF_OPMODE] = 0x04, + [PLL_OFF_STATUS] = 0x0c, + [PLL_OFF_L_VAL] = 0x10, + [PLL_OFF_USER_CTL] = 0x14, + [PLL_OFF_USER_CTL_U] = 0x18, + [PLL_OFF_CONFIG_CTL] = 0x1c, + [PLL_OFF_CONFIG_CTL_U] = 0x20, + [PLL_OFF_CONFIG_CTL_U1] = 0x24, + [PLL_OFF_TEST_CTL] = 0x28, + [PLL_OFF_TEST_CTL_U] = 0x2c, + }, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); @@ -2179,3 +2191,61 @@ const struct clk_ops clk_alpha_pll_lucid_evo_ops = { .set_rate = alpha_pll_lucid_5lpe_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops); + +void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, + const struct alpha_pll_config *config) +{ + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); + clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); + clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); + clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); + + regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); + + regmap_update_bits(regmap, PLL_MODE(pll), + PLL_RESET_N | PLL_BYPASSNL | PLL_OUTCTRL, + PLL_RESET_N | PLL_BYPASSNL); +} +EXPORT_SYMBOL_GPL(clk_rivian_evo_pll_configure); + +static unsigned long clk_rivian_evo_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + u32 l; + + regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); + + return parent_rate * l; +} + +static long clk_rivian_evo_pll_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + unsigned long min_freq, max_freq; + u32 l; + u64 a; + + rate = alpha_pll_round_rate(rate, *prate, &l, &a, 0); + if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) + return rate; + + min_freq = pll->vco_table[0].min_freq; + max_freq = pll->vco_table[pll->num_vco - 1].max_freq; + + return clamp(rate, min_freq, max_freq); +} + +const struct clk_ops clk_alpha_pll_rivian_evo_ops = { + .enable = alpha_pll_lucid_5lpe_enable, + .disable = alpha_pll_lucid_5lpe_disable, + .is_enabled = clk_trion_pll_is_enabled, + .recalc_rate = clk_rivian_evo_pll_recalc_rate, + .round_rate = clk_rivian_evo_pll_round_rate, +}; +EXPORT_SYMBOL_GPL(clk_alpha_pll_rivian_evo_ops); diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 0b7a6859ca2c..447efb82fe59 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -18,6 +18,7 @@ enum { CLK_ALPHA_PLL_TYPE_AGERA, CLK_ALPHA_PLL_TYPE_ZONDA, CLK_ALPHA_PLL_TYPE_LUCID_EVO, + CLK_ALPHA_PLL_TYPE_RIVIAN_EVO, CLK_ALPHA_PLL_TYPE_MAX, }; @@ -157,6 +158,9 @@ extern const struct clk_ops clk_alpha_pll_lucid_evo_ops; extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops; extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops; +extern const struct clk_ops clk_alpha_pll_rivian_evo_ops; +#define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_ops + void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config); void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, @@ -172,5 +176,7 @@ void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config); void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config); +void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, + const struct alpha_pll_config *config); #endif