diff mbox series

[v2,5/6] arm64: dts: qcom: Fix 'reg-names' for sdhci nodes

Message ID 20220514215424.1007718-6-bhupesh.sharma@linaro.org (mailing list archive)
State Accepted
Headers show
Series arm64: dts: qcom: Fix 'sdhci' nodes for 'make dtbs_check' | expand

Commit Message

Bhupesh Sharma May 14, 2022, 9:54 p.m. UTC 
Since the Qualcomm sdhci-msm device-tree binding has been converted
to yaml format, 'make dtbs_check' reports a number of issues with
ordering of 'reg-names' as various possible combinations
are possible for different qcom SoC dts files.

Fix the same by updating the offending 'dts' files.

Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
 arch/arm64/boot/dts/qcom/qcs404.dtsi | 2 +-
 arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +-
 arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +-
 arch/arm64/boot/dts/qcom/sdm630.dtsi | 4 ++--
 arch/arm64/boot/dts/qcom/sm6125.dtsi | 4 ++--
 arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +-
 6 files changed, 8 insertions(+), 8 deletions(-)

Comments

Doug Anderson July 6, 2022, 9:48 p.m. UTC | #1 
Hi,

On Sat, May 14, 2022 at 2:55 PM Bhupesh Sharma
<bhupesh.sharma@linaro.org> wrote:
>
> Since the Qualcomm sdhci-msm device-tree binding has been converted
> to yaml format, 'make dtbs_check' reports a number of issues with
> ordering of 'reg-names' as various possible combinations
> are possible for different qcom SoC dts files.
>
> Fix the same by updating the offending 'dts' files.
>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Rob Herring <robh@kernel.org>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> ---
>  arch/arm64/boot/dts/qcom/qcs404.dtsi | 2 +-
>  arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +-
>  arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +-
>  arch/arm64/boot/dts/qcom/sdm630.dtsi | 4 ++--
>  arch/arm64/boot/dts/qcom/sm6125.dtsi | 4 ++--
>  arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +-
>  6 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> index 86dbf8ea04bc..45044083faf0 100644
> --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> @@ -792,7 +792,7 @@ pcie_phy: phy@7786000 {
>                 sdcc1: mmc@7804000 {
>                         compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5";
>                         reg = <0x07804000 0x1000>, <0x7805000 0x1000>;
> -                       reg-names = "hc", "cqhci";
> +                       reg-names = "hc_mem", "cqe_mem";
>
>                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
>                                      <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index 9076892ff4f8..08f2decc7f4f 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -697,7 +697,7 @@ sdhc_1: mmc@7c4000 {
>                         compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
>                         reg = <0 0x7c4000 0 0x1000>,
>                                 <0 0x07c5000 0 0x1000>;
> -                       reg-names = "hc", "cqhci";
> +                       reg-names = "hc_mem", "cqe_mem";
>
>                         iommus = <&apps_smmu 0x60 0x0>;
>                         interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index e63d1a4499f8..eaaccf0184af 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -866,7 +866,7 @@ sdhc_1: mmc@7c4000 {
>
>                         reg = <0 0x007c4000 0 0x1000>,
>                               <0 0x007c5000 0 0x1000>;
> -                       reg-names = "hc", "cqhci";
> +                       reg-names = "hc_mem", "cqe_mem";

Yer breakin' mah build!

The second register here (and probably all boards) needs to be
"cqhci". See the line in the driver that looks like:

/* check and setup CMDQ interface */
cqhci_memres = platform_get_resource_byname(pdev, IORESOURCE_MEM,
                                           "cqhci");

For history, see commit d3392339cae9 ("mmc: cqhci: Update cqhci memory
ioresource name") and commit d79100c91ae5 ("dt-bindings: mmc:
sdhci-msm: Add CQE reg map").

The problem here is not the device trees but the yaml. When you
convert from .txt to .yaml you're not allowed to just rewrite the
binding. It should also be noted that the "_mem" suffix was explicitly
requested to be removed.

Revert posted at:
https://lore.kernel.org/r/20220706144706.1.I48f35820bf3670d54940110462555c2d0a6d5eb2@changeid
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index 86dbf8ea04bc..45044083faf0 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -792,7 +792,7 @@  pcie_phy: phy@7786000 {
 		sdcc1: mmc@7804000 {
 			compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5";
 			reg = <0x07804000 0x1000>, <0x7805000 0x1000>;
-			reg-names = "hc", "cqhci";
+			reg-names = "hc_mem", "cqe_mem";
 
 			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 9076892ff4f8..08f2decc7f4f 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -697,7 +697,7 @@  sdhc_1: mmc@7c4000 {
 			compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
 			reg = <0 0x7c4000 0 0x1000>,
 				<0 0x07c5000 0 0x1000>;
-			reg-names = "hc", "cqhci";
+			reg-names = "hc_mem", "cqe_mem";
 
 			iommus = <&apps_smmu 0x60 0x0>;
 			interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index e63d1a4499f8..eaaccf0184af 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -866,7 +866,7 @@  sdhc_1: mmc@7c4000 {
 
 			reg = <0 0x007c4000 0 0x1000>,
 			      <0 0x007c5000 0 0x1000>;
-			reg-names = "hc", "cqhci";
+			reg-names = "hc_mem", "cqe_mem";
 
 			iommus = <&apps_smmu 0xc0 0x0>;
 			interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>,
diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi
index 6d872e2f400a..77dc985b3634 100644
--- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
@@ -1275,7 +1275,7 @@  qusb2phy: phy@c012000 {
 		sdhc_2: mmc@c084000 {
 			compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
 			reg = <0x0c084000 0x1000>;
-			reg-names = "hc";
+			reg-names = "hc_mem";
 
 			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 					<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
@@ -1330,7 +1330,7 @@  sdhc_1: mmc@c0c4000 {
 			reg = <0x0c0c4000 0x1000>,
 			      <0x0c0c5000 0x1000>,
 			      <0x0c0c8000 0x8000>;
-			reg-names = "hc", "cqhci", "ice";
+			reg-names = "hc_mem", "cqe_mem", "ice_mem";
 
 			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 					<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
index 77bff81af433..94e427abbfd2 100644
--- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
@@ -438,7 +438,7 @@  rpm_msg_ram: sram@45f0000 {
 		sdhc_1: mmc@4744000 {
 			compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
 			reg = <0x04744000 0x1000>, <0x04745000 0x1000>;
-			reg-names = "hc", "core";
+			reg-names = "hc_mem", "core_mem";
 
 			interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
@@ -459,7 +459,7 @@  sdhc_1: mmc@4744000 {
 		sdhc_2: mmc@4784000 {
 			compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
 			reg = <0x04784000 0x1000>;
-			reg-names = "hc";
+			reg-names = "hc_mem";
 
 			interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 1b1eb884136b..6d959aa0ea94 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -477,7 +477,7 @@  sdhc_1: mmc@7c4000 {
 			reg = <0 0x007c4000 0 0x1000>,
 				<0 0x007c5000 0 0x1000>,
 				<0 0x007c8000 0 0x8000>;
-			reg-names = "hc", "cqhci", "ice";
+			reg-names = "hc_mem", "cqe_mem", "ice_mem";
 
 			interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;