| Message ID | 20220515210048.483898-1-robimarko@gmail.com (mailing list archive) |
|---|---|
| State | Accepted |
| Headers | show |
| Series | [v4,01/11] clk: qcom: ipq8074: fix NSS core PLL-s | expand |
On Sun, 15 May 2022 23:00:38 +0200, Robert Marko wrote: > Like in IPQ6018 the NSS related Alpha PLL-s require initial configuration > to work. > > So, obtain the regmap that is required for the Alpha PLL configuration > and thus utilize the qcom_cc_really_probe() as we already have the regmap. > Then utilize the Alpha PLL configs from the downstream QCA 5.4 based > kernel to configure them. > > [...] Applied, thanks! [01/11] clk: qcom: ipq8074: fix NSS core PLL-s commit: ca41ec1b30434636c56c5600b24a8d964d359d9c [02/11] clk: qcom: ipq8074: SW workaround for UBI32 PLL lock commit: 3401ea2856ef84f39b75f0dc5ebcaeda81cb90ec [03/11] clk: qcom: ipq8074: fix NSS port frequency tables commit: 0e9e61a2815b5cd34f1b495b2d72e8127ce9b794 [04/11] dt-bindings: clock: qcom: ipq8074: add PPE crypto clock commit: 90e6d290603df6387c95c114cc8154862c3e7515 [05/11] clk: qcom: ipq8074: add PPE crypto clock commit: 74521205b64030b1321ccc04372729cfd2800996 [06/11] clk: qcom: ipq8074: set BRANCH_HALT_DELAY flag for UBI clocks commit: 2bd357e698207e2e65db03007e4be65bf9d6a7b3 [07/11] dt-bindings: clocks: qcom,gcc-ipq8074: support power domains commit: 2c930dc1e34f08d32ccf1b2baf01dec56b41ab05 [08/11] dt-bindings: clock: qcom: ipq8074: add USB GDSCs commit: 74622e401e2109a9aacce0b9698bbcd2307db17a [09/11] clk: qcom: ipq8074: add USB GDSCs commit: 8add990ace3db767c2dab59113fbdf137d237529 [10/11] clk: qcom: ipq8074: dont disable gcc_sleep_clk_src commit: 1bf7305e79aab095196131bdc87a97796e0e3fac Best regards,
diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index 541016db3c4b..1a5141da7e23 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -4371,6 +4371,33 @@ static struct clk_branch gcc_pcie0_axi_s_bridge_clk = { }, }; +static const struct alpha_pll_config ubi32_pll_config = { + .l = 0x4e, + .config_ctl_val = 0x200d4aa8, + .config_ctl_hi_val = 0x3c2, + .main_output_mask = BIT(0), + .aux_output_mask = BIT(1), + .pre_div_val = 0x0, + .pre_div_mask = BIT(12), + .post_div_val = 0x0, + .post_div_mask = GENMASK(9, 8), +}; + +static const struct alpha_pll_config nss_crypto_pll_config = { + .l = 0x3e, + .alpha = 0x0, + .alpha_hi = 0x80, + .config_ctl_val = 0x4001055b, + .main_output_mask = BIT(0), + .pre_div_val = 0x0, + .pre_div_mask = GENMASK(14, 12), + .post_div_val = 0x1 << 8, + .post_div_mask = GENMASK(11, 8), + .vco_mask = GENMASK(21, 20), + .vco_val = 0x0, + .alpha_en_mask = BIT(24), +}; + static struct clk_hw *gcc_ipq8074_hws[] = { &gpll0_out_main_div2.hw, &gpll6_out_main_div2.hw, @@ -4772,7 +4799,17 @@ static const struct qcom_cc_desc gcc_ipq8074_desc = { static int gcc_ipq8074_probe(struct platform_device *pdev) { - return qcom_cc_probe(pdev, &gcc_ipq8074_desc); + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &gcc_ipq8074_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config); + clk_alpha_pll_configure(&nss_crypto_pll_main, regmap, + &nss_crypto_pll_config); + + return qcom_cc_really_probe(pdev, &gcc_ipq8074_desc, regmap); } static struct platform_driver gcc_ipq8074_driver = {
Like in IPQ6018 the NSS related Alpha PLL-s require initial configuration to work. So, obtain the regmap that is required for the Alpha PLL configuration and thus utilize the qcom_cc_really_probe() as we already have the regmap. Then utilize the Alpha PLL configs from the downstream QCA 5.4 based kernel to configure them. This fixes the UBI32 and NSS crypto PLL-s failing to get enabled by the kernel. Fixes: b8e7e519625f ("clk: qcom: ipq8074: add remaining PLL’s") Signed-off-by: Robert Marko <robimarko@gmail.com> --- drivers/clk/qcom/gcc-ipq8074.c | 39 +++++++++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-)