diff mbox series

[1/3] ARM: dts: qcom: sdx55: Fix the IRQ trigger type for UART

Message ID 20220530080842.37024-2-manivannan.sadhasivam@linaro.org (mailing list archive)
State Accepted
Headers show
Series Check for IRQ trigger type mismatch in __setup_irq() | expand

Commit Message

Manivannan Sadhasivam May 30, 2022, 8:08 a.m. UTC 
The trigger type should be LEVEL_HIGH. So fix it!

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 arch/arm/boot/dts/qcom-sdx55.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Bjorn Andersson July 3, 2022, 3:56 a.m. UTC | #1 
On Mon, 30 May 2022 13:38:40 +0530, Manivannan Sadhasivam wrote:
> The trigger type should be LEVEL_HIGH. So fix it!
> 
> 

Applied, thanks!

[1/3] ARM: dts: qcom: sdx55: Fix the IRQ trigger type for UART
      commit: ae500b351ab0006d933d804a2b7507fe1e98cecc

Best regards,
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi
index d455795da44c..b75e672c239d 100644
--- a/arch/arm/boot/dts/qcom-sdx55.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx55.dtsi
@@ -206,7 +206,7 @@  gcc: clock-controller@100000 {
 		blsp1_uart3: serial@831000 {
 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 			reg = <0x00831000 0x200>;
-			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_LOW>;
+			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&gcc 30>,
 				 <&gcc 9>;
 			clock-names = "core", "iface";