From patchwork Fri Jun 10 08:45:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nuno Sa X-Patchwork-Id: 12876880 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18D8CC43334 for ; Fri, 10 Jun 2022 08:49:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348415AbiFJItc (ORCPT ); Fri, 10 Jun 2022 04:49:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48624 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348431AbiFJItH (ORCPT ); Fri, 10 Jun 2022 04:49:07 -0400 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D33EBF5520; Fri, 10 Jun 2022 01:49:04 -0700 (PDT) Received: from pps.filterd (m0167089.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 25A7SjCl005350; Fri, 10 Jun 2022 04:49:04 -0400 Received: from nwd2mta3.analog.com ([137.71.173.56]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 3ghq33kqe3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 10 Jun 2022 04:49:04 -0400 Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta3.analog.com (8.14.7/8.14.7) with ESMTP id 25A8n3Kt023331 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 10 Jun 2022 04:49:03 -0400 Received: from ASHBCASHYB4.ad.analog.com (10.64.17.132) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 10 Jun 2022 04:49:02 -0400 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBCASHYB4.ad.analog.com (10.64.17.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 10 Jun 2022 04:49:02 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Fri, 10 Jun 2022 04:49:02 -0400 Received: from nsa.ad.analog.com ([10.44.3.70]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 25A8imir014275; Fri, 10 Jun 2022 04:48:50 -0400 From: =?utf-8?q?Nuno_S=C3=A1?= To: , , , , , Lad Prabhakar , , , , , CC: Cai Huoqing , Benjamin Fair , Jishnu Prakash , "Linus Walleij" , Lars-Peter Clausen , Alexandre Torgue , Amit Kucheria , Andy Gross , Michael Hennerich , Haibo Chen , Benson Leung , "Rafael J. Wysocki" , "Alexandre Belloni" , Christophe Branchereau , Patrick Venture , Arnd Bergmann , Nancy Yuen , Sascha Hauer , Daniel Lezcano , "Gwendal Grignou" , Saravanan Sekar , "Tali Perry" , Maxime Coquelin , Paul Cercueil , Thara Gopinath , Avi Fishman , "Lorenzo Bianconi" , Claudiu Beznea , Pengutronix Kernel Team , Andy Shevchenko , Fabrice Gasnier , Matthias Brugger , Tomer Maimon , Bjorn Andersson , "Nicolas Ferre" , Jonathan Cameron , Zhang Rui , Shawn Guo , "Guenter Roeck" , Fabio Estevam , "Olivier Moysan" , Eugen Hristev , Miquel Raynal Subject: [PATCH 31/34] iio: adc: qcom-spmi-adc5: convert to device properties Date: Fri, 10 Jun 2022 10:45:42 +0200 Message-ID: <20220610084545.547700-32-nuno.sa@analog.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220610084545.547700-1-nuno.sa@analog.com> References: <20220610084545.547700-1-nuno.sa@analog.com> MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: lRX3q1Sm_9npDIyKIT-3VhvZf79E_QQX X-Proofpoint-GUID: lRX3q1Sm_9npDIyKIT-3VhvZf79E_QQX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-10_02,2022-06-09_02,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxlogscore=999 phishscore=0 priorityscore=1501 adultscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 spamscore=0 impostorscore=0 bulkscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2204290000 definitions=main-2206100032 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Make the conversion to firmware agnostic device properties. As part of the conversion the IIO inkern interface 'of_xlate()' is also converted to 'fwnode_xlate()'. The goal is to completely drop 'of_xlate' and hence OF dependencies from IIO. Signed-off-by: Nuno Sá Acked-by: Linus Walleij --- drivers/iio/adc/qcom-spmi-adc5.c | 63 +++++++++++++++----------------- 1 file changed, 30 insertions(+), 33 deletions(-) diff --git a/drivers/iio/adc/qcom-spmi-adc5.c b/drivers/iio/adc/qcom-spmi-adc5.c index 87438d1e5c0b..a23f9293d6c1 100644 --- a/drivers/iio/adc/qcom-spmi-adc5.c +++ b/drivers/iio/adc/qcom-spmi-adc5.c @@ -14,9 +14,9 @@ #include #include #include -#include -#include +#include #include +#include #include #include @@ -403,8 +403,8 @@ static irqreturn_t adc5_isr(int irq, void *dev_id) return IRQ_HANDLED; } -static int adc5_of_xlate(struct iio_dev *indio_dev, - const struct of_phandle_args *iiospec) +static int adc5_fwnode_xlate(struct iio_dev *indio_dev, + const struct fwnode_reference_args *iiospec) { struct adc5_chip *adc = iio_priv(indio_dev); int i; @@ -416,8 +416,8 @@ static int adc5_of_xlate(struct iio_dev *indio_dev, return -EINVAL; } -static int adc7_of_xlate(struct iio_dev *indio_dev, - const struct of_phandle_args *iiospec) +static int adc7_fwnode_xlate(struct iio_dev *indio_dev, + const struct fwnode_reference_args *iiospec) { struct adc5_chip *adc = iio_priv(indio_dev); int i, v_channel; @@ -481,12 +481,12 @@ static int adc7_read_raw(struct iio_dev *indio_dev, static const struct iio_info adc5_info = { .read_raw = adc5_read_raw, - .of_xlate = adc5_of_xlate, + .fwnode_xlate = adc5_fwnode_xlate, }; static const struct iio_info adc7_info = { .read_raw = adc7_read_raw, - .of_xlate = adc7_of_xlate, + .fwnode_xlate = adc7_fwnode_xlate, }; struct adc5_channels { @@ -611,18 +611,18 @@ static const struct adc5_channels adc5_chans_rev2[ADC5_MAX_CHANNEL] = { SCALE_HW_CALIB_THERM_100K_PULLUP) }; -static int adc5_get_dt_channel_data(struct adc5_chip *adc, +static int adc5_get_fw_channel_data(struct adc5_chip *adc, struct adc5_channel_prop *prop, - struct device_node *node, + struct fwnode_handle *fwnode, const struct adc5_data *data) { - const char *name = node->name, *channel_name; + const char *name = fwnode_get_name(fwnode), *channel_name; u32 chan, value, varr[2]; u32 sid = 0; int ret; struct device *dev = adc->dev; - ret = of_property_read_u32(node, "reg", &chan); + ret = fwnode_property_read_u32(fwnode, "reg", &chan); if (ret) { dev_err(dev, "invalid channel number %s\n", name); return ret; @@ -647,15 +647,13 @@ static int adc5_get_dt_channel_data(struct adc5_chip *adc, prop->channel = chan; prop->sid = sid; - channel_name = of_get_property(node, - "label", NULL) ? : node->name; - if (!channel_name) { - dev_err(dev, "Invalid channel name\n"); - return -EINVAL; - } + ret = fwnode_property_read_string(fwnode, "label", &channel_name); + if (ret) + channel_name = name; + prop->datasheet_name = channel_name; - ret = of_property_read_u32(node, "qcom,decimation", &value); + ret = fwnode_property_read_u32(fwnode, "qcom,decimation", &value); if (!ret) { ret = qcom_adc5_decimation_from_dt(value, data->decimation); if (ret < 0) { @@ -668,7 +666,7 @@ static int adc5_get_dt_channel_data(struct adc5_chip *adc, prop->decimation = ADC5_DECIMATION_DEFAULT; } - ret = of_property_read_u32_array(node, "qcom,pre-scaling", varr, 2); + ret = fwnode_property_read_u32_array(fwnode, "qcom,pre-scaling", varr, 2); if (!ret) { ret = qcom_adc5_prescaling_from_dt(varr[0], varr[1]); if (ret < 0) { @@ -682,7 +680,7 @@ static int adc5_get_dt_channel_data(struct adc5_chip *adc, adc->data->adc_chans[prop->channel].prescale_index; } - ret = of_property_read_u32(node, "qcom,hw-settle-time", &value); + ret = fwnode_property_read_u32(fwnode, "qcom,hw-settle-time", &value); if (!ret) { u8 dig_version[2]; @@ -713,7 +711,7 @@ static int adc5_get_dt_channel_data(struct adc5_chip *adc, prop->hw_settle_time = VADC_DEF_HW_SETTLE_TIME; } - ret = of_property_read_u32(node, "qcom,avg-samples", &value); + ret = fwnode_property_read_u32(fwnode, "qcom,avg-samples", &value); if (!ret) { ret = qcom_adc5_avg_samples_from_dt(value); if (ret < 0) { @@ -726,7 +724,7 @@ static int adc5_get_dt_channel_data(struct adc5_chip *adc, prop->avg_samples = VADC_DEF_AVG_SAMPLES; } - if (of_property_read_bool(node, "qcom,ratiometric")) + if (fwnode_property_read_bool(fwnode, "qcom,ratiometric")) prop->cal_method = ADC5_RATIOMETRIC_CAL; else prop->cal_method = ADC5_ABSOLUTE_CAL; @@ -801,16 +799,16 @@ static const struct of_device_id adc5_match_table[] = { }; MODULE_DEVICE_TABLE(of, adc5_match_table); -static int adc5_get_dt_data(struct adc5_chip *adc, struct device_node *node) +static int adc5_get_fw_data(struct adc5_chip *adc) { const struct adc5_channels *adc_chan; struct iio_chan_spec *iio_chan; struct adc5_channel_prop prop, *chan_props; - struct device_node *child; + struct fwnode_handle *child; unsigned int index = 0; int ret; - adc->nchannels = of_get_available_child_count(node); + adc->nchannels = device_get_child_node_count(adc->dev); if (!adc->nchannels) return -EINVAL; @@ -826,14 +824,14 @@ static int adc5_get_dt_data(struct adc5_chip *adc, struct device_node *node) chan_props = adc->chan_props; iio_chan = adc->iio_chans; - adc->data = of_device_get_match_data(adc->dev); + adc->data = device_get_match_data(adc->dev); if (!adc->data) adc->data = &adc5_data_pmic; - for_each_available_child_of_node(node, child) { - ret = adc5_get_dt_channel_data(adc, &prop, child, adc->data); + device_for_each_child_node(adc->dev, child) { + ret = adc5_get_fw_channel_data(adc, &prop, child, adc->data); if (ret) { - of_node_put(child); + fwnode_handle_put(child); return ret; } @@ -858,7 +856,6 @@ static int adc5_get_dt_data(struct adc5_chip *adc, struct device_node *node) static int adc5_probe(struct platform_device *pdev) { - struct device_node *node = pdev->dev.of_node; struct device *dev = &pdev->dev; struct iio_dev *indio_dev; struct adc5_chip *adc; @@ -870,7 +867,7 @@ static int adc5_probe(struct platform_device *pdev) if (!regmap) return -ENODEV; - ret = of_property_read_u32(node, "reg", ®); + ret = device_property_read_u32(dev, "reg", ®); if (ret < 0) return ret; @@ -886,7 +883,7 @@ static int adc5_probe(struct platform_device *pdev) init_completion(&adc->complete); mutex_init(&adc->lock); - ret = adc5_get_dt_data(adc, node); + ret = adc5_get_fw_data(adc); if (ret) { dev_err(dev, "adc get dt data failed\n"); return ret;