From patchwork Wed Jun 22 21:58:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Joseph S. Barrera III" X-Patchwork-Id: 12891533 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D81A8CCA479 for ; Wed, 22 Jun 2022 21:59:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244606AbiFVV7s (ORCPT ); Wed, 22 Jun 2022 17:59:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44302 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1356081AbiFVV7h (ORCPT ); Wed, 22 Jun 2022 17:59:37 -0400 Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 38A1E1BEB8 for ; Wed, 22 Jun 2022 14:59:25 -0700 (PDT) Received: by mail-pj1-x1032.google.com with SMTP id x1-20020a17090abc8100b001ec7f8a51f5so727515pjr.0 for ; Wed, 22 Jun 2022 14:59:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uf+HuQ1ItIoNqZupwoKpU9pz3NkBB1lHPNxwiXXD+2w=; b=hyxmfFfu07K7sLrUw5QkwMAAH5ndrOSwzb2F+Qa+rgiNxY+si7NLFnfB4OUCOWIn10 oN8ExJ2bMCOMfo4CtAEf+AfYnDH/WOFG3JKiDvfLcVhXnAVlySyYE+t+eUsGWusIEax9 wrzbT1hbSVVVYlWdmVa1sU+zx14CnhZTAgavA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uf+HuQ1ItIoNqZupwoKpU9pz3NkBB1lHPNxwiXXD+2w=; b=LW38YoGspjtrFvYHDCeLHUnoS0E342LqVHFU48gAH4ezTwANn8E3af1kCY7u0Npc8M HizAnKmCcuXnpgC795wpuXCcrS8ZUhdcAc6vDRdqRMKwJ6JW46TWbFWgdUfihWdACsB0 +ZsNeGFv1pwJ+TK09zhkdcLgN5j4SdjPyxYLsM1AwV9wbMny1ey3ZzfXK4NWIgtxs4Jt 4OMXKG/m48BkSkxWW9Tqngt3DDh/vUooWdh7bkHjuO8O6i0ZyXoussgRxihrcQU0yH7g wQO/WuvwBTo1+jECAwFVI7v9ygrBQN26VBcQBT2Kq2nHoXQqcRtH0C0kEqNad8tAS4oe ZuAg== X-Gm-Message-State: AJIora84RAk7SMJnbATEIrFueN+7Y9gBZhkbSVVfJxkvQTtwWPGYWCdd fCFzNnZzGe/wH0vst5XBpflilw== X-Google-Smtp-Source: AGRyM1sYH7FA2SAitMGkc4Qvvg1WF3u1cjELIfHo5tVKuKUjc52erulNEgjNcztldxbzadeP7bTMIA== X-Received: by 2002:a17:903:228c:b0:16a:24d7:6a9e with SMTP id b12-20020a170903228c00b0016a24d76a9emr17618429plh.27.1655935164423; Wed, 22 Jun 2022 14:59:24 -0700 (PDT) Received: from joebar-glaptop.lan (c-71-202-34-56.hsd1.ca.comcast.net. [71.202.34.56]) by smtp.gmail.com with ESMTPSA id nk15-20020a17090b194f00b001ec9d45776bsm255916pjb.42.2022.06.22.14.59.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jun 2022 14:59:23 -0700 (PDT) From: "Joseph S. Barrera III" To: LKML Cc: Stephen Boyd , Douglas Anderson , Alexandru M Stan , "Joseph S. Barrera III" , Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v10 4/5] arm64: dts: qcom: sc7180: Add pazquel dts files Date: Wed, 22 Jun 2022 14:58:04 -0700 Message-Id: <20220622145717.v10.4.I41e2c2dc12961fe000ebc4d4ef6f0bc5da1259ea@changeid> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20220622215805.1121982-1-joebar@chromium.org> References: <20220622215805.1121982-1-joebar@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Pazquel is a trogdor-based board. These dts files are unchanged copies from the downstream Chrome OS 5.4 kernel. Signed-off-by: Joseph S. Barrera III --- Changes in v10: - Remove 'include sc7180.dtsi' from *all* sc7180-trogdor-pazquel* files. - Move "okay" for ap_tp_i2c to proper location. Changes in v9: - Restore two lines accidentally removed from ap_sar_sensor. - Simplify trackpad enabling (51d30402be75). Changes in v7: - Only include sc7180.dtsi in sc7180-trogdor.dtsi (19794489fa24). - Simplify spi0/spi6 labeling (d277cab7afc7). - Remove #include of . - Accidentally removed two lines from ap_sar_sensor. Changes in v6: - Copy changes to ap_sar_sensor from v5.4. - Add #include of . Changes in v4: - Fix description (no downstream bits removed). - Add missing version history. Changes in v3: - First inclusion in series. arch/arm64/boot/dts/qcom/Makefile | 4 + .../sc7180-trogdor-pazquel-lte-parade.dts | 21 ++ .../qcom/sc7180-trogdor-pazquel-lte-ti.dts | 21 ++ .../qcom/sc7180-trogdor-pazquel-parade.dts | 16 ++ .../dts/qcom/sc7180-trogdor-pazquel-ti.dts | 16 ++ .../boot/dts/qcom/sc7180-trogdor-pazquel.dtsi | 221 ++++++++++++++++++ 6 files changed, 299 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-lte-parade.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-lte-ti.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-parade.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-ti.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 5cfd6316768c..dc26704dfe34 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -79,6 +79,10 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-mrbland-rev0-auo.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-mrbland-rev0-boe.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-mrbland-rev1-auo.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-mrbland-rev1-boe.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-lte-parade.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-lte-ti.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-parade.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-ti.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r2.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-lte-parade.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-lte-parade.dts new file mode 100644 index 000000000000..407adca19652 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-lte-parade.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Pazquel board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180-trogdor-parade-ps8640.dtsi" +#include "sc7180-trogdor-pazquel.dtsi" +#include "sc7180-trogdor-lte-sku.dtsi" + +/ { + model = "Google Pazquel (Parade,LTE)"; + compatible = "google,pazquel-sku4", "qcom,sc7180"; +}; + +&ap_sar_sensor_i2c { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-lte-ti.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-lte-ti.dts new file mode 100644 index 000000000000..857877cf1565 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-lte-ti.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Pazquel board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180-trogdor-ti-sn65dsi86.dtsi" +#include "sc7180-trogdor-pazquel.dtsi" +#include "sc7180-trogdor-lte-sku.dtsi" + +/ { + model = "Google Pazquel (TI,LTE)"; + compatible = "google,pazquel-sku0", "google,pazquel-sku2", "qcom,sc7180"; +}; + +&ap_sar_sensor_i2c { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-parade.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-parade.dts new file mode 100644 index 000000000000..f28c6c7f522c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-parade.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Pazquel board device tree source + * + * Copyright 2022 Google LLC. + */ + +/dts-v1/; + +#include "sc7180-trogdor-parade-ps8640.dtsi" +#include "sc7180-trogdor-pazquel.dtsi" + +/ { + model = "Google Pazquel (Parade)"; + compatible = "google,pazquel-sku5", "qcom,sc7180"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-ti.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-ti.dts new file mode 100644 index 000000000000..9f950f596fa1 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-ti.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Pazquel board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180-trogdor-ti-sn65dsi86.dtsi" +#include "sc7180-trogdor-pazquel.dtsi" + +/ { + model = "Google Pazquel (TI)"; + compatible = "google,pazquel-sku1", "qcom,sc7180"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi new file mode 100644 index 000000000000..5e4731b24d34 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi @@ -0,0 +1,221 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Pazquel board device tree source + * + * Copyright 2021 Google LLC. + */ + +#include "sc7180-trogdor.dtsi" + +&ap_sar_sensor { + compatible = "semtech,sx9324"; + semtech,ph0-pin = <1 3 3>; + semtech,ph1-pin = <3 1 3>; + semtech,ph2-pin = <1 3 3>; + semtech,ph3-pin = <0 0 0>; + semtech,ph01-resolution = <1024>; + semtech,ph23-resolution = <1024>; + semtech,startup-sensor = <1>; + semtech,ph01-proxraw-strength = <3>; + semtech,ph23-proxraw-strength = <1>; + semtech,avg-pos-strength = <128>; + semtech,input-analog-gain = <0>; + semtech,cs-idle-sleep = "gnd"; + + /delete-property/ svdd-supply; + vdd-supply = <&pp1800_prox>; +}; + +/delete-node/&trackpad; +&ap_tp_i2c { + status = "okay"; + trackpad: trackpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + pinctrl-names = "default"; + pinctrl-0 = <&tp_int_odl>; + + interrupt-parent = <&tlmm>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + + vcc-supply = <&pp3300_fp_tp>; + post-power-on-delay-ms = <100>; + hid-descr-addr = <0x0001>; + + wakeup-source; + }; +}; + +&keyboard_controller { + function-row-physmap = < + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + >; + linux,keymap = < + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) + MATRIX_KEY(0x02, 0x02, KEY_ZOOM) + MATRIX_KEY(0x01, 0x02, KEY_SCALE) + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x02, 0x09, KEY_MUTE) + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) + CROS_STD_MAIN_KEYMAP + >; +}; + +&panel { + compatible = "edp-panel"; +}; + +&pp3300_dx_edp { + gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>; +}; + +&en_pp3300_dx_edp { + pinmux { + pins = "gpio67"; + }; + + pinconf { + pins = "gpio67"; + }; +}; + +/* PINCTRL - board-specific pinctrl */ + +&tlmm { + gpio-line-names = "TP_INT_ODL", + "AP_RAM_ID0", + "AP_SKU_ID2", + "AP_RAM_ID1", + "", + "AP_RAM_ID2", + "AP_TP_I2C_SDA", + "AP_TP_I2C_SCL", + "TS_RESET_L", + "TS_INT_L", + "", + "EDP_BRIJ_IRQ", + "AP_EDP_BKLTEN", + "", + "", + "EDP_BRIJ_I2C_SDA", + "EDP_BRIJ_I2C_SCL", + "HUB_RST_L", + "", + "", + "", + "", + "", + "AMP_EN", + "P_SENSOR_INT_L", + "AP_SAR_SENSOR_SDA", + "AP_SAR_SENSOR_SCL", + "", + "HP_IRQ", + "", + "", + "AP_BRD_ID2", + "BRIJ_SUSPEND", + "AP_BRD_ID0", + "AP_H1_SPI_MISO", + "AP_H1_SPI_MOSI", + "AP_H1_SPI_CLK", + "AP_H1_SPI_CS_L", + "", + "", + "", + "", + "H1_AP_INT_ODL", + "", + "UART_AP_TX_DBG_RX", + "UART_DBG_TX_AP_RX", + "HP_I2C_SDA", + "HP_I2C_SCL", + "FORCED_USB_BOOT", + "AMP_BCLK", + "AMP_LRCLK", + "AMP_DIN", + "", + "HP_BCLK", + "HP_LRCLK", + "HP_DOUT", + "HP_DIN", + "HP_MCLK", + "AP_SKU_ID0", + "AP_EC_SPI_MISO", + "AP_EC_SPI_MOSI", + "AP_EC_SPI_CLK", + "AP_EC_SPI_CS_L", + "AP_SPI_CLK", + "AP_SPI_MOSI", + "AP_SPI_MISO", + /* + * AP_FLASH_WP_L is crossystem ABI. Schematics + * call it BIOS_FLASH_WP_L. + */ + "AP_FLASH_WP_L", + "EN_PP3300_DX_EDP", + "AP_SPI_CS0_L", + "", + "", + "", + "", + "", + "", + "UIM2_DATA", + "UIM2_CLK", + "UIM2_RST", + "UIM2_PRESENT", + "UIM1_DATA", + "UIM1_CLK", + "UIM1_RST", + "", + "CODEC_PWR_EN", + "HUB_EN", + "", + "", + "", + "", + "", + "AP_SKU_ID1", + "AP_RST_REQ", + "", + "AP_BRD_ID1", + "AP_EC_INT_L", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "EDP_BRIJ_EN", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "AP_TS_PEN_I2C_SDA", + "AP_TS_PEN_I2C_SCL", + "DP_HOT_PLUG_DET", + "EC_IN_RW_ODL"; +};