[v1,4/4] arm64: dts: qcom: sm8450: add display clock controller

Commit Message

Dmitry Baryshkov June 23, 2022, 11:47 a.m. UTC

Add device node for display clock controller on Qualcomm SM8450 platform

Signed-off-by: Dmitry Baryshkov <[e-mail]>
---
 arch/arm64/boot/dts/qcom/sm8450.dtsi | 35 ++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

Patch

diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 7d08fad76371..4fb60aef77f4 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -4,6 +4,7 @@ 
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,dispcc-sm8450.h>
 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/dma/qcom-gpi.h>
@@ -2288,6 +2289,40 @@  IPCC_MPROC_SIGNAL_GLINK_QMP
 			};
 		};
 
+		dispcc: clock-controller@af00000 {
+			compatible = "qcom,sm8450-dispcc";
+			reg = <0 0x0af00000 0 0x20000>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK_A>,
+				 <0>, <0>,
+				 <0>, <0>,
+				 <0>, <0>,
+				 <0>, <0>,
+				 <0>, <0>,
+				 <0>, <0>,
+				 <&sleep_clk>;
+			clock-names = "bi_tcxo",
+				      "bi_tcxo_ao",
+				      "dsi0_phy_pll_out_byteclk",
+				      "dsi0_phy_pll_out_dsiclk",
+				      "dsi1_phy_pll_out_byteclk",
+				      "dsi1_phy_pll_out_dsiclk",
+				      "dp0_phy_pll_link_clk",
+				      "dp0_phy_pll_vco_div_clk",
+				      "dp1_phy_pll_link_clk",
+				      "dp1_phy_pll_vco_div_clk",
+				      "dp2_phy_pll_link_clk",
+				      "dp2_phy_pll_vco_div_clk",
+				      "dp3_phy_pll_link_clk",
+				      "dp3_phy_pll_vco_div_clk",
+				      "sleep_clk";
+			power-domains = <&rpmhpd SM8450_MMCX>;
+			required-opps = <&rpmhpd_opp_low_svs>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
 		pdc: interrupt-controller@b220000 {
 			compatible = "qcom,sm8450-pdc", "qcom,pdc";
 			reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;