From patchwork Fri Jun 24 12:00:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Zapolskiy X-Patchwork-Id: 12894417 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06341C43334 for ; Fri, 24 Jun 2022 12:00:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230425AbiFXMAI (ORCPT ); Fri, 24 Jun 2022 08:00:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48744 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231387AbiFXMAG (ORCPT ); Fri, 24 Jun 2022 08:00:06 -0400 Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [IPv6:2a00:1450:4864:20::129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5163977046 for ; Fri, 24 Jun 2022 05:00:05 -0700 (PDT) Received: by mail-lf1-x129.google.com with SMTP id t24so4092310lfr.4 for ; Fri, 24 Jun 2022 05:00:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=m6ETYuJ3k+Mw8/Wb7Txo0YU1MR9fbOxsatXnGmKpvrI=; b=mnbCqPgaJRfZRL+f+iT59Q8cEoMxcdkDwjQtWfSIEyygF3it/WZP38xLHcSPu2FY3a k6Wu/smlvY7HWU3DDOL7jH/JItNMouG6Slk8FwVSlkw7gPK+ZyA5dLM0p4pkhEkdAuU0 OGFAgjeXtitHKSiQN75eH/+qSIsMYy9BpH2CDke+Wj9dNzsc+TT1qvfBezaIpWkSmdQr eZsJcswcKVHSug9uowDak53N2PfdowxPGeUNvQMf6cN68siXrmwUWG4V1zJPVf69o79/ tcDDawTIAflvIV28tuJ+uY+XbBSzPej82O4lLOM2aWWB1M8S222PdSxwSgX/Q4Etm1vS sK+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=m6ETYuJ3k+Mw8/Wb7Txo0YU1MR9fbOxsatXnGmKpvrI=; b=W8hsfghk5zWT6nMIxYZ+MfzSlRK8mWcTurb1nXyjAUOOwrpKoElMxbH/PlNdhQz/xI exl6+CF/Xpa55ms2Dg4ip0VHWgNZ6YIiRSVMsyS5tW7gKKMOLToOBQ8LibYxNWD5HXfO X702xORwYTxn0zzaq0c3E/U8n5ndGvba7k4oo2b987ws7cT8xeD5qCDUiTzxFEEVovcr YQmPub5eGKZcyE+9Idw8aV+E+B35sDFUiQylJmnTzGnbtlhwnomb7HzlLLphUZgqo5mV pRYak7u5IKNvOV+ViDKn+Q8n9TreBYO+ZouAcmf5rui9ofecDEJ1V2ntx3xuotZUwYnG jieA== X-Gm-Message-State: AJIora9+z7b6mjSxm3zGlZvxCHrNb3XMo4ZsISKv51AV4Gg89N8WJIFx 1tj++ZiiWdJPk/fQbJH45KTZoA== X-Google-Smtp-Source: AGRyM1tRhxvX3iHVAFOW+WHxUrB1R2t8Dic+87xjxgq/usCme8JaskWLs+semjl0JAk130jpOhNjzg== X-Received: by 2002:a05:6512:3502:b0:47f:4d1f:9378 with SMTP id h2-20020a056512350200b0047f4d1f9378mr8639422lfs.357.1656072004833; Fri, 24 Jun 2022 05:00:04 -0700 (PDT) Received: from localhost.localdomain (88-112-131-206.elisa-laajakaista.fi. [88.112.131.206]) by smtp.gmail.com with ESMTPSA id z7-20020a2e3507000000b0025a7f1065fdsm250492ljz.107.2022.06.24.05.00.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jun 2022 05:00:04 -0700 (PDT) From: Vladimir Zapolskiy To: Bjorn Andersson Cc: Andy Gross , Stephen Boyd , Michael Turquette , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v8 5/7] clk: qcom: clk-alpha-pll: add Lucid EVO PLL configuration interfaces Date: Fri, 24 Jun 2022 15:00:03 +0300 Message-Id: <20220624120003.2524930-1-vladimir.zapolskiy@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220624115917.2524868-1-vladimir.zapolskiy@linaro.org> References: <20220624115917.2524868-1-vladimir.zapolskiy@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add controls for Lucid EVO PLL configuration and export control functions to clock controller drivers. Signed-off-by: Vladimir Zapolskiy --- Changes from v7 to v8: * improved commit message per request from Stephen. Changes from v3 to v7: * none. Changes from v2 to v3: * improved commit subject and description per ask from Bjorn. Changes from v1 to v2: * none drivers/clk/qcom/clk-alpha-pll.c | 64 ++++++++++++++++++++++++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 5 ++- 2 files changed, 68 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 47879ee5a677..cdb1035ae3ed 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -191,8 +191,10 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); #define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21) /* LUCID EVO PLL specific settings and offsets */ +#define LUCID_EVO_PCAL_NOT_DONE BIT(8) #define LUCID_EVO_ENABLE_VOTE_RUN BIT(25) #define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0) +#define LUCID_EVO_PLL_CAL_L_VAL_SHIFT 16 /* ZONDA PLL specific */ #define ZONDA_PLL_OUT_MASK 0xf @@ -1994,6 +1996,32 @@ const struct clk_ops clk_alpha_pll_zonda_ops = { }; EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops); +void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, + const struct alpha_pll_config *config) +{ + u32 lval = config->l; + + lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT; + clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval); + clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); + clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); + clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); + + /* Disable PLL output */ + regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); + + /* Set operation mode to STANDBY and de-assert the reset */ + regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); + regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); +} +EXPORT_SYMBOL_GPL(clk_lucid_evo_pll_configure); + static int alpha_pll_lucid_evo_enable(struct clk_hw *hw) { struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); @@ -2079,6 +2107,31 @@ static void alpha_pll_lucid_evo_disable(struct clk_hw *hw) regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); } +static int alpha_pll_lucid_evo_prepare(struct clk_hw *hw) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + struct clk_hw *p; + u32 val = 0; + int ret; + + /* Return early if calibration is not needed. */ + regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); + if (!(val & LUCID_EVO_PCAL_NOT_DONE)) + return 0; + + p = clk_hw_get_parent(hw); + if (!p) + return -EINVAL; + + ret = alpha_pll_lucid_evo_enable(hw); + if (ret) + return ret; + + alpha_pll_lucid_evo_disable(hw); + + return 0; +} + static unsigned long alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -2114,3 +2167,14 @@ const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops = { .set_rate = clk_lucid_evo_pll_postdiv_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_evo_ops); + +const struct clk_ops clk_alpha_pll_lucid_evo_ops = { + .prepare = alpha_pll_lucid_evo_prepare, + .enable = alpha_pll_lucid_evo_enable, + .disable = alpha_pll_lucid_evo_disable, + .is_enabled = clk_trion_pll_is_enabled, + .recalc_rate = alpha_pll_lucid_evo_recalc_rate, + .round_rate = clk_alpha_pll_round_rate, + .set_rate = alpha_pll_lucid_5lpe_set_rate, +}; +EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops); diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 6e9907deaf30..0b7a6859ca2c 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -152,6 +152,8 @@ extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops; extern const struct clk_ops clk_alpha_pll_zonda_ops; #define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops + +extern const struct clk_ops clk_alpha_pll_lucid_evo_ops; extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops; extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops; @@ -168,6 +170,7 @@ void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config); - +void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, + const struct alpha_pll_config *config); #endif