diff mbox series

[01/14] arm64: dts: qcom: sc7280: drop PCIe PHY clock index

Message ID 20220705114032.22787-2-johan+linaro@kernel.org (mailing list archive)
State Queued
Headers show
Series arm64: dts: qcom: QMP PHY fixes | expand

Commit Message

Johan Hovold July 5, 2022, 11:40 a.m. UTC
The QMP PCIe PHY provides a single clock so drop the redundant clock
index.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
---
 arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Dmitry Baryshkov July 5, 2022, 11:57 a.m. UTC | #1
On 05/07/2022 14:40, Johan Hovold wrote:
> The QMP PCIe PHY provides a single clock so drop the redundant clock
> index.
> 
> Signed-off-by: Johan Hovold <johan+linaro@kernel.org>

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

> ---
>   arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
Dmitry Baryshkov July 5, 2022, 12:42 p.m. UTC | #2
On 05/07/2022 14:40, Johan Hovold wrote:
> The QMP PCIe PHY provides a single clock so drop the redundant clock
> index.
> 
> Signed-off-by: Johan Hovold <johan+linaro@kernel.org>

Hmm. After checking the source code, the clocks entry of the phy@1c0e000 
node also needs to be fixed.

And also maybe:

Fixes: bd7d507935ca ("arm64: dts: qcom: sc7280: Add pcie clock support")
Fixes: 92e0ee9f83b3 ("arm64: dts: qcom: sc7280: Add PCIe and PHY related 
nodes")


> ---
>   arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index e66fc67de206..b0ae2dbba50f 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -818,7 +818,7 @@ gcc: clock-controller@100000 {
>   			reg = <0 0x00100000 0 0x1f0000>;
>   			clocks = <&rpmhcc RPMH_CXO_CLK>,
>   				 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
> -				 <0>, <&pcie1_lane 0>,
> +				 <0>, <&pcie1_lane>,
>   				 <0>, <0>, <0>, <0>;
>   			clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
>   				      "pcie_0_pipe_clk", "pcie_1_pipe_clk",
> @@ -2110,7 +2110,7 @@ pcie1_lane: phy@1c0e200 {
>   				clock-names = "pipe0";
>   
>   				#phy-cells = <0>;
> -				#clock-cells = <1>;
> +				#clock-cells = <0>;
>   				clock-output-names = "pcie_1_pipe_clk";
>   			};
>   		};
Johan Hovold July 5, 2022, 12:51 p.m. UTC | #3
On Tue, Jul 05, 2022 at 03:42:08PM +0300, Dmitry Baryshkov wrote:
> On 05/07/2022 14:40, Johan Hovold wrote:
> > The QMP PCIe PHY provides a single clock so drop the redundant clock
> > index.
> > 
> > Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
> 
> Hmm. After checking the source code, the clocks entry of the phy@1c0e000 
> node also needs to be fixed.

I assume you meant pci@1c08000 here? Thanks for catching that!

> And also maybe:
> 
> Fixes: bd7d507935ca ("arm64: dts: qcom: sc7280: Add pcie clock support")
> Fixes: 92e0ee9f83b3 ("arm64: dts: qcom: sc7280: Add PCIe and PHY related 
> nodes")

Maybe, I'm a bit reluctant to add a Fixes tags for these even if they do
violate the binding. But sure, why not.

> > ---
> >   arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 ++--
> >   1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > index e66fc67de206..b0ae2dbba50f 100644
> > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > @@ -818,7 +818,7 @@ gcc: clock-controller@100000 {
> >   			reg = <0 0x00100000 0 0x1f0000>;
> >   			clocks = <&rpmhcc RPMH_CXO_CLK>,
> >   				 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
> > -				 <0>, <&pcie1_lane 0>,
> > +				 <0>, <&pcie1_lane>,
> >   				 <0>, <0>, <0>, <0>;
> >   			clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
> >   				      "pcie_0_pipe_clk", "pcie_1_pipe_clk",
> > @@ -2110,7 +2110,7 @@ pcie1_lane: phy@1c0e200 {
> >   				clock-names = "pipe0";
> >   
> >   				#phy-cells = <0>;
> > -				#clock-cells = <1>;
> > +				#clock-cells = <0>;
> >   				clock-output-names = "pcie_1_pipe_clk";
> >   			};
> >   		};

Johan
Dmitry Baryshkov July 5, 2022, 12:57 p.m. UTC | #4
On Tue, 5 Jul 2022 at 15:51, Johan Hovold <johan@kernel.org> wrote:
>
> On Tue, Jul 05, 2022 at 03:42:08PM +0300, Dmitry Baryshkov wrote:
> > On 05/07/2022 14:40, Johan Hovold wrote:
> > > The QMP PCIe PHY provides a single clock so drop the redundant clock
> > > index.
> > >
> > > Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
> >
> > Hmm. After checking the source code, the clocks entry of the phy@1c0e000
> > node also needs to be fixed.
>
> I assume you meant pci@1c08000 here? Thanks for catching that!
>
> > And also maybe:
> >
> > Fixes: bd7d507935ca ("arm64: dts: qcom: sc7280: Add pcie clock support")
> > Fixes: 92e0ee9f83b3 ("arm64: dts: qcom: sc7280: Add PCIe and PHY related
> > nodes")
>
> Maybe, I'm a bit reluctant to add a Fixes tags for these even if they do
> violate the binding. But sure, why not.

Yep, I'm also in doubt here. In this case this is more logical. I'd
allow you to decide then.

>
> > > ---
> > >   arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 ++--
> > >   1 file changed, 2 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > > index e66fc67de206..b0ae2dbba50f 100644
> > > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > > @@ -818,7 +818,7 @@ gcc: clock-controller@100000 {
> > >                     reg = <0 0x00100000 0 0x1f0000>;
> > >                     clocks = <&rpmhcc RPMH_CXO_CLK>,
> > >                              <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
> > > -                            <0>, <&pcie1_lane 0>,
> > > +                            <0>, <&pcie1_lane>,
> > >                              <0>, <0>, <0>, <0>;
> > >                     clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
> > >                                   "pcie_0_pipe_clk", "pcie_1_pipe_clk",
> > > @@ -2110,7 +2110,7 @@ pcie1_lane: phy@1c0e200 {
> > >                             clock-names = "pipe0";
> > >
> > >                             #phy-cells = <0>;
> > > -                           #clock-cells = <1>;
> > > +                           #clock-cells = <0>;
> > >                             clock-output-names = "pcie_1_pipe_clk";
> > >                     };
> > >             };
>
> Johan
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index e66fc67de206..b0ae2dbba50f 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -818,7 +818,7 @@  gcc: clock-controller@100000 {
 			reg = <0 0x00100000 0 0x1f0000>;
 			clocks = <&rpmhcc RPMH_CXO_CLK>,
 				 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
-				 <0>, <&pcie1_lane 0>,
+				 <0>, <&pcie1_lane>,
 				 <0>, <0>, <0>, <0>;
 			clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
 				      "pcie_0_pipe_clk", "pcie_1_pipe_clk",
@@ -2110,7 +2110,7 @@  pcie1_lane: phy@1c0e200 {
 				clock-names = "pipe0";
 
 				#phy-cells = <0>;
-				#clock-cells = <1>;
+				#clock-cells = <0>;
 				clock-output-names = "pcie_1_pipe_clk";
 			};
 		};