diff mbox series

[1/3] dt-bindings: display/msm: Add binding for SC8280XP MDSS

Message ID 20220811040121.3775613-2-bjorn.andersson@linaro.org (mailing list archive)
State Not Applicable
Headers show
Series drm/msm/dpu: Add support for SC8280XP | expand

Commit Message

Bjorn Andersson Aug. 11, 2022, 4:01 a.m. UTC
Add binding for the display subsystem and display processing unit in the
Qualcomm SC8280XP platform.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
 .../bindings/display/msm/dpu-sc8280xp.yaml    | 284 ++++++++++++++++++
 1 file changed, 284 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-sc8280xp.yaml

Comments

Krzysztof Kozlowski Aug. 11, 2022, 7:56 a.m. UTC | #1
On 11/08/2022 07:01, Bjorn Andersson wrote:
> Add binding for the display subsystem and display processing unit in the
> Qualcomm SC8280XP platform.
> 
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
>  .../bindings/display/msm/dpu-sc8280xp.yaml    | 284 ++++++++++++++++++
>  1 file changed, 284 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-sc8280xp.yaml
> 
> diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc8280xp.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sc8280xp.yaml
> new file mode 100644
> index 000000000000..6c25943e639c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/dpu-sc8280xp.yaml

qcom prefix is needed (also when file is in msm subdir)

The file name should be based on compatible, so "qcom,sc8280xp-mdss.yaml"

> @@ -0,0 +1,284 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/msm/dpu-sc8280xp.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Display Processing Unit for SC8280XP
> +
> +maintainers:
> +  - Bjorn Andersson <bjorn.andersson@linaro.org>
> +
> +description:
> +  Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates
> +  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
> +  bindings of MDSS and DPU are mentioned for SC8280XP.

s/Device tree bindings//
so just:

SC8280XP MSM Mobile Display Subsystem (MDSS) that encapsulates
sub-blocks like DPU display controller, DSI and DP interfaces etc.

> +
> +properties:
> +  compatible:
> +    const: qcom,sc8280xp-mdss
> +
> +  reg:
> +    maxItems: 1
> +
> +  reg-names:
> +    const: mdss

You do not need reg names for one item, especially if the name is kind
of obvious... unless you re-use existing driver which needs it? Then
maybe let's change the driver to take first element?

> +
> +  power-domains:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: Display AHB clock from gcc
> +      - description: Display AHB clock from dispcc
> +      - description: Display core clock
> +
> +  clock-names:
> +    items:
> +      - const: iface
> +      - const: ahb
> +      - const: core
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  interrupt-controller: true
> +
> +  "#address-cells": true
> +
> +  "#size-cells": true

I see other DPU bindings also specify both as "true". Why not a fixed
number (const)?

> +
> +  "#interrupt-cells":
> +    const: 1
> +
> +  iommus:
> +    items:
> +      - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
> +
> +  ranges: true
> +
> +  interconnects:
> +    minItems: 2

No need for minItems in such case.

> +    maxItems: 2
> +
> +  interconnect-names:
> +    items:
> +      - const: mdp0-mem
> +      - const: mdp1-mem
> +
> +  resets:
> +    items:
> +      - description: MDSS_CORE reset
> +
> +patternProperties:
> +  "^display-controller@[0-9a-f]+$":
> +    type: object
> +    description: Node containing the properties of DPU.

additionalProperties:false on this level

which will point to missing properties (e.g. opp-table)

> +
> +    properties:
> +      compatible:
> +        const: qcom,sc8280xp-dpu
> +


Best regards,
Krzysztof
Krzysztof Kozlowski Aug. 11, 2022, 8:04 a.m. UTC | #2
On 11/08/2022 10:56, Krzysztof Kozlowski wrote:
> On 11/08/2022 07:01, Bjorn Andersson wrote:
>> Add binding for the display subsystem and display processing unit in the
>> Qualcomm SC8280XP platform.
>>
>> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
>> ---
>>  .../bindings/display/msm/dpu-sc8280xp.yaml    | 284 ++++++++++++++++++
>>  1 file changed, 284 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-sc8280xp.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc8280xp.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sc8280xp.yaml
>> new file mode 100644
>> index 000000000000..6c25943e639c
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/display/msm/dpu-sc8280xp.yaml
> 
> qcom prefix is needed (also when file is in msm subdir)
> 
> The file name should be based on compatible, so "qcom,sc8280xp-mdss.yaml"
> 
>> @@ -0,0 +1,284 @@
>> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/display/msm/dpu-sc8280xp.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm Display Processing Unit for SC8280XP
>> +
>> +maintainers:
>> +  - Bjorn Andersson <bjorn.andersson@linaro.org>
>> +
>> +description:
>> +  Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates
>> +  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
>> +  bindings of MDSS and DPU are mentioned for SC8280XP.
> 
> s/Device tree bindings//
> so just:
> 
> SC8280XP MSM Mobile Display Subsystem (MDSS) that encapsulates
> sub-blocks like DPU display controller, DSI and DP interfaces etc.
> 
>> +
>> +properties:
>> +  compatible:
>> +    const: qcom,sc8280xp-mdss
>> +
>> +  reg:
>> +    maxItems: 1
>> +
>> +  reg-names:
>> +    const: mdss
> 
> You do not need reg names for one item, especially if the name is kind
> of obvious... unless you re-use existing driver which needs it? Then
> maybe let's change the driver to take first element?

OK, I see the driver expects this. It seems it is legacy from
87729e2a7871 ("drm/msm: unify MDSS drivers") times. So it could be
changed to grab first element always (older MDSS with three reg items
still has mdss_phys at first item).

> 
>> +
>> +  power-domains:
>> +    maxItems: 1
>> +
>> +  clocks:
>> +    items:
>> +      - description: Display AHB clock from gcc
>> +      - description: Display AHB clock from dispcc
>> +      - description: Display core clock
>> +
>> +  clock-names:
>> +    items:
>> +      - const: iface
>> +      - const: ahb
>> +      - const: core
>> +
>> +  interrupts:
>> +    maxItems: 1
>> +
>> +  interrupt-controller: true
>> +
>> +  "#address-cells": true
>> +
>> +  "#size-cells": true
> 
> I see other DPU bindings also specify both as "true". Why not a fixed
> number (const)?
> 
>> +
>> +  "#interrupt-cells":
>> +    const: 1
>> +
>> +  iommus:
>> +    items:
>> +      - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
>> +
>> +  ranges: true
>> +
>> +  interconnects:
>> +    minItems: 2
> 
> No need for minItems in such case.
> 
>> +    maxItems: 2
>> +
>> +  interconnect-names:
>> +    items:
>> +      - const: mdp0-mem
>> +      - const: mdp1-mem
>> +
>> +  resets:
>> +    items:
>> +      - description: MDSS_CORE reset
>> +
>> +patternProperties:
>> +  "^display-controller@[0-9a-f]+$":
>> +    type: object
>> +    description: Node containing the properties of DPU.
> 
> additionalProperties:false on this level
> 
> which will point to missing properties (e.g. opp-table)

I'll fix existing bindings which have similar issue.


Best regards,
Krzysztof
Krzysztof Kozlowski Aug. 11, 2022, 8:26 a.m. UTC | #3
On 11/08/2022 11:04, Krzysztof Kozlowski wrote:
>>
>> additionalProperties:false on this level
>>
>> which will point to missing properties (e.g. opp-table)
> 
> I'll fix existing bindings which have similar issue.

Hm, I think Dmitry is already working on this:
https://lore.kernel.org/all/20220710090040.35193-5-dmitry.baryshkov@linaro.org/
so your patches should be on top of his.


Best regards,
Krzysztof
Rob Herring (Arm) Aug. 12, 2022, 3:13 p.m. UTC | #4
On Wed, 10 Aug 2022 21:01:19 -0700, Bjorn Andersson wrote:
> Add binding for the display subsystem and display processing unit in the
> Qualcomm SC8280XP platform.
> 
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
>  .../bindings/display/msm/dpu-sc8280xp.yaml    | 284 ++++++++++++++++++
>  1 file changed, 284 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-sc8280xp.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/display/msm/dpu-sc8280xp.example.dts:21:18: fatal error: dt-bindings/clock/qcom,dispcc-sc8280xp.h: No such file or directory
   21 |         #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
      |                  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:383: Documentation/devicetree/bindings/display/msm/dpu-sc8280xp.example.dtb] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1404: dt_binding_check] Error 2

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc8280xp.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sc8280xp.yaml
new file mode 100644
index 000000000000..6c25943e639c
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/dpu-sc8280xp.yaml
@@ -0,0 +1,284 @@ 
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/dpu-sc8280xp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display Processing Unit for SC8280XP
+
+maintainers:
+  - Bjorn Andersson <bjorn.andersson@linaro.org>
+
+description:
+  Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates
+  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
+  bindings of MDSS and DPU are mentioned for SC8280XP.
+
+properties:
+  compatible:
+    const: qcom,sc8280xp-mdss
+
+  reg:
+    maxItems: 1
+
+  reg-names:
+    const: mdss
+
+  power-domains:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: Display AHB clock from gcc
+      - description: Display AHB clock from dispcc
+      - description: Display core clock
+
+  clock-names:
+    items:
+      - const: iface
+      - const: ahb
+      - const: core
+
+  interrupts:
+    maxItems: 1
+
+  interrupt-controller: true
+
+  "#address-cells": true
+
+  "#size-cells": true
+
+  "#interrupt-cells":
+    const: 1
+
+  iommus:
+    items:
+      - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
+
+  ranges: true
+
+  interconnects:
+    minItems: 2
+    maxItems: 2
+
+  interconnect-names:
+    items:
+      - const: mdp0-mem
+      - const: mdp1-mem
+
+  resets:
+    items:
+      - description: MDSS_CORE reset
+
+patternProperties:
+  "^display-controller@[0-9a-f]+$":
+    type: object
+    description: Node containing the properties of DPU.
+
+    properties:
+      compatible:
+        const: qcom,sc8280xp-dpu
+
+      reg:
+        items:
+          - description: Address offset and size for mdp register set
+          - description: Address offset and size for vbif register set
+
+      reg-names:
+        items:
+          - const: mdp
+          - const: vbif
+
+      clocks:
+        items:
+          - description: Display hf axi clock
+          - description: Display sf axi clock
+          - description: Display ahb clock
+          - description: Display lut clock
+          - description: Display core clock
+          - description: Display vsync clock
+
+      clock-names:
+        items:
+          - const: bus
+          - const: nrt_bus
+          - const: iface
+          - const: lut
+          - const: core
+          - const: vsync
+
+      interrupts:
+        maxItems: 1
+
+      power-domains:
+        maxItems: 1
+
+      operating-points-v2: true
+
+      ports:
+        $ref: /schemas/graph.yaml#/properties/ports
+        description: |
+          Contains the list of output ports from DPU device. These ports
+          connect to interfaces that are external to the DPU hardware,
+          such as DSI, DP etc. Each output port contains an endpoint that
+          describes how it is connected to an external interface.
+
+        patternProperties:
+          '^port@[0-8]$':
+            $ref: /schemas/graph.yaml#/properties/port
+            description: DPU interfaces
+
+    required:
+      - compatible
+      - reg
+      - reg-names
+      - clocks
+      - interrupts
+      - power-domains
+      - operating-points-v2
+      - ports
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - power-domains
+  - clocks
+  - interrupts
+  - interrupt-controller
+  - iommus
+  - ranges
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
+    #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interconnect/qcom,sc8280xp.h>
+    #include <dt-bindings/power/qcom-rpmpd.h>
+
+    display-subsystem@ae00000 {
+      compatible = "qcom,sc8280xp-mdss";
+      reg = <0x0ae00000 0x1000>;
+      reg-names = "mdss";
+
+      power-domains = <&dispcc0 MDSS_GDSC>;
+
+      clocks = <&gcc GCC_DISP_AHB_CLK>,
+               <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
+               <&dispcc0 DISP_CC_MDSS_MDP_CLK>;
+      clock-names = "iface",
+                    "ahb",
+                    "core";
+
+      assigned-clocks = <&dispcc0 DISP_CC_MDSS_MDP_CLK>;
+      assigned-clock-rates = <460000000>;
+
+      resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>;
+
+      interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+      interrupt-controller;
+      #interrupt-cells = <1>;
+
+      interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
+                      <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
+      interconnect-names = "mdp0-mem", "mdp1-mem";
+
+      iommus = <&apps_smmu 0x1000 0x402>;
+
+      #address-cells = <1>;
+      #size-cells = <1>;
+      ranges;
+
+      display-controller@ae01000 {
+        compatible = "qcom,sc8280xp-dpu";
+        reg = <0x0ae01000 0x8f000>,
+              <0x0aeb0000 0x2008>;
+        reg-names = "mdp", "vbif";
+
+        clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+                 <&gcc GCC_DISP_SF_AXI_CLK>,
+                 <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
+                 <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>,
+                 <&dispcc0 DISP_CC_MDSS_MDP_CLK>,
+                 <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
+        clock-names = "bus",
+                      "nrt_bus",
+                      "iface",
+                      "lut",
+                      "core",
+                      "vsync";
+
+        assigned-clocks = <&dispcc0 DISP_CC_MDSS_MDP_CLK>,
+                          <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
+        assigned-clock-rates = <460000000>,
+                               <19200000>;
+
+        operating-points-v2 = <&mdss0_mdp_opp_table>;
+        power-domains = <&rpmhpd SC8280XP_MMCX>;
+
+        interrupt-parent = <&mdss0>;
+        interrupts = <0>;
+
+        ports {
+          #address-cells = <1>;
+          #size-cells = <0>;
+
+          port@0 {
+            reg = <0>;
+              endpoint {
+                remote-endpoint = <&mdss0_dp0_in>;
+              };
+          };
+
+          port@4 {
+            reg = <4>;
+            endpoint {
+              remote-endpoint = <&mdss0_dp1_in>;
+            };
+          };
+
+          port@5 {
+            reg = <5>;
+              endpoint {
+                remote-endpoint = <&mdss0_dp3_in>;
+              };
+          };
+
+          port@6 {
+            reg = <6>;
+              endpoint {
+                remote-endpoint = <&mdss0_dp2_in>;
+              };
+          };
+        };
+
+        mdss0_mdp_opp_table: opp-table {
+          compatible = "operating-points-v2";
+
+          opp-200000000 {
+            opp-hz = /bits/ 64 <200000000>;
+            required-opps = <&rpmhpd_opp_low_svs>;
+          };
+
+          opp-300000000 {
+            opp-hz = /bits/ 64 <300000000>;
+            required-opps = <&rpmhpd_opp_svs>;
+          };
+
+          opp-345000000 {
+            opp-hz = /bits/ 64 <345000000>;
+            required-opps = <&rpmhpd_opp_svs_l1>;
+          };
+
+          opp-460000000 {
+            opp-hz = /bits/ 64 <460000000>;
+            required-opps = <&rpmhpd_opp_nom>;
+          };
+        };
+      };
+    };
+...
+