Message ID | 20220826071244.185584-1-ebiggers@kernel.org (mailing list archive) |
---|---|
State | Accepted |
Commit | 276ee34a40c1440544f609b54b23b99ead8f2205 |
Headers | show |
Series | arm64: dts: qcom: sm8450: add Inline Crypto Engine registers and clock | expand |
On 26.08.2022 09:12, Eric Biggers wrote: > From: Eric Biggers <ebiggers@google.com> > > Add the registers and clock for the Inline Crypto Engine (ICE) to the > device tree node for the UFS host controller on sm8450. This makes > ufs_qcom support inline encryption when CONFIG_SCSI_UFS_CRYPTO=y. > > The address and size of the register range, and the minimum and maximum > frequency of the ICE core clock, all match the values used downstream. > > I've validated this on an SM8450 HDK using the 'encrypt' group of > xfstests on ext4 with MOUNT_OPTIONS="-o inlinecrypt". > > Signed-off-by: Eric Biggers <ebiggers@google.com> > --- dt-bindings needs an update to allow the second reg. For this patch, however: Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Konrad > arch/arm64/boot/dts/qcom/sm8450.dtsi | 13 +++++++++---- > 1 file changed, 9 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi > index 4978c5ba5dd085..517b3a1fbe7c04 100644 > --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi > @@ -3069,7 +3069,9 @@ system-cache-controller@19200000 { > ufs_mem_hc: ufshc@1d84000 { > compatible = "qcom,sm8450-ufshc", "qcom,ufshc", > "jedec,ufs-2.0"; > - reg = <0 0x01d84000 0 0x3000>; > + reg = <0 0x01d84000 0 0x3000>, > + <0 0x01d88000 0 0x8000>; > + reg-names = "std", "ice"; > interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; > phys = <&ufs_mem_phy_lanes>; > phy-names = "ufsphy"; > @@ -3093,7 +3095,8 @@ ufs_mem_hc: ufshc@1d84000 { > "ref_clk", > "tx_lane0_sync_clk", > "rx_lane0_sync_clk", > - "rx_lane1_sync_clk"; > + "rx_lane1_sync_clk", > + "ice_core_clk"; > clocks = > <&gcc GCC_UFS_PHY_AXI_CLK>, > <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, > @@ -3102,7 +3105,8 @@ ufs_mem_hc: ufshc@1d84000 { > <&rpmhcc RPMH_CXO_CLK>, > <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, > <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, > - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; > + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, > + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; > freq-table-hz = > <75000000 300000000>, > <0 0>, > @@ -3111,7 +3115,8 @@ ufs_mem_hc: ufshc@1d84000 { > <75000000 300000000>, > <0 0>, > <0 0>, > - <0 0>; > + <0 0>, > + <75000000 300000000>; > status = "disabled"; > }; > > > base-commit: 1c23f9e627a7b412978b4e852793c5e3c3efc555
On Fri, 26 Aug 2022 00:12:44 -0700, Eric Biggers wrote: > From: Eric Biggers <ebiggers@google.com> > > Add the registers and clock for the Inline Crypto Engine (ICE) to the > device tree node for the UFS host controller on sm8450. This makes > ufs_qcom support inline encryption when CONFIG_SCSI_UFS_CRYPTO=y. > > The address and size of the register range, and the minimum and maximum > frequency of the ICE core clock, all match the values used downstream. > > [...] Applied, thanks! [1/1] arm64: dts: qcom: sm8450: add Inline Crypto Engine registers and clock commit: 276ee34a40c1440544f609b54b23b99ead8f2205 Best regards,
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 4978c5ba5dd085..517b3a1fbe7c04 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -3069,7 +3069,9 @@ system-cache-controller@19200000 { ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sm8450-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; - reg = <0 0x01d84000 0 0x3000>; + reg = <0 0x01d84000 0 0x3000>, + <0 0x01d88000 0 0x8000>; + reg-names = "std", "ice"; interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; phys = <&ufs_mem_phy_lanes>; phy-names = "ufsphy"; @@ -3093,7 +3095,8 @@ ufs_mem_hc: ufshc@1d84000 { "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk", - "rx_lane1_sync_clk"; + "rx_lane1_sync_clk", + "ice_core_clk"; clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, @@ -3102,7 +3105,8 @@ ufs_mem_hc: ufshc@1d84000 { <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; freq-table-hz = <75000000 300000000>, <0 0>, @@ -3111,7 +3115,8 @@ ufs_mem_hc: ufshc@1d84000 { <75000000 300000000>, <0 0>, <0 0>, - <0 0>; + <0 0>, + <75000000 300000000>; status = "disabled"; };