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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Sep 2022 08:24:57.1982 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2aab0ddb-ed9f-4596-e82e-08da9561716a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.236];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT032.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6463 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The clock is not symmetrically disabled in the error-out routines. Fixes: 109bd48ea2e1 ("iommu/msm: Add DT adaptation") Cc: stable@vger.kernel.org Cc: Sricharan R Cc: Andy Gross Cc: Bjorn Andersson Cc: Konrad Dybcio Signed-off-by: Nicolin Chen --- drivers/iommu/msm_iommu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/iommu/msm_iommu.c b/drivers/iommu/msm_iommu.c index 6a24aa804ea3..a7d41ba4a47b 100644 --- a/drivers/iommu/msm_iommu.c +++ b/drivers/iommu/msm_iommu.c @@ -418,6 +418,7 @@ static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) list_for_each_entry(master, &iommu->ctx_list, list) { if (master->num) { dev_err(dev, "domain already attached"); + __disable_clocks(iommu); ret = -EEXIST; goto fail; } @@ -425,6 +426,7 @@ static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) msm_iommu_alloc_ctx(iommu->context_map, 0, iommu->ncb); if (IS_ERR_VALUE(master->num)) { + __disable_clocks(iommu); ret = -ENODEV; goto fail; }