From patchwork Tue Oct 11 13:14:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 13003992 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39649C433F5 for ; Tue, 11 Oct 2022 13:15:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229980AbiJKNPA (ORCPT ); Tue, 11 Oct 2022 09:15:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36158 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229815AbiJKNOx (ORCPT ); Tue, 11 Oct 2022 09:14:53 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7FA981057C; Tue, 11 Oct 2022 06:14:49 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id B34E861197; Tue, 11 Oct 2022 13:14:48 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 69A57C43142; Tue, 11 Oct 2022 13:14:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1665494087; bh=eiGmm82gpFRQdkb3KdRgApBkCTz0Bg7w4vO6cpM6XK4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IhFvt0JzLs7RVpg5j9IGicNF40mf2sTe1YAF5cT1VXt3NRQp+76/R/DtZSlsZEQFJ 9oSAJSKQQ4MDjZ6sInhnf0rN4x9tRXvoR4opMXP5vysMo1Lykboy+3CAqA5EjFvwwk XXcIVbfPxmmvL+Hi71+ahLP/q7M7ebBzMRDdhHx2ydL5ivgZheTpLygKUCV1bV97s/ PYHq9zSLtUSTcccWgp+WQUqULq6cNLNFDrgpV9LrMAKIHT/lK99+rn4J2g2ysGRQpU uFh2l6DWqPnYNjaZ1ECHPJJk1bbAdNG6ZOsIQ51/u3jDHafrujwFMpEKm8gDMvHBcw vTowyLGdXhXhw== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1oiF5i-0000ez-U8; Tue, 11 Oct 2022 15:14:38 +0200 From: Johan Hovold To: Vinod Koul Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Kishon Vijay Abraham I , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH 09/13] phy: qcom-qmp-pcie-msm8996: drop power-down delay config Date: Tue, 11 Oct 2022 15:14:12 +0200 Message-Id: <20221011131416.2478-10-johan+linaro@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221011131416.2478-1-johan+linaro@kernel.org> References: <20221011131416.2478-1-johan+linaro@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The power-down delay was included in the first version of the QMP driver for MSM8996 as an optional delay after powering on the PHY (using POWER_DOWN_CONTROL) and just before starting it. Later changes modified this sequence by powering on before initialising the PHY, but the optional delay stayed where it was (i.e. before starting the PHY). The vendor driver does not use a delay before starting the PHY and this is likely not needed on any platform unless there is a corresponding delay in the vendor kernel init sequence tables (i.e. in devicetree). Let's keep the delay for now, but drop the redundant configuration options while increasing the unnecessarily low timer slack somewhat. Signed-off-by: Johan Hovold Reviewed-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c index 31ac405d3785..899be7bd4d92 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c @@ -41,7 +41,7 @@ #define PHY_INIT_COMPLETE_TIMEOUT 10000 #define POWER_DOWN_DELAY_US_MIN 10 -#define POWER_DOWN_DELAY_US_MAX 11 +#define POWER_DOWN_DELAY_US_MAX 20 struct qmp_phy_init_tbl { unsigned int offset; @@ -203,12 +203,6 @@ struct qmp_phy_cfg { unsigned int mask_com_pcs_ready; /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ unsigned int phy_status; - - /* true, if PHY needs delay after POWER_DOWN */ - bool has_pwrdn_delay; - /* power_down delay in usec */ - int pwrdn_delay_min; - int pwrdn_delay_max; }; /** @@ -326,10 +320,6 @@ static const struct qmp_phy_cfg msm8996_pciephy_cfg = { .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .mask_com_pcs_ready = PCS_READY, .phy_status = PHYSTATUS, - - .has_pwrdn_delay = true, - .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, - .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, }; static void qmp_pcie_msm8996_configure_lane(void __iomem *base, @@ -523,8 +513,7 @@ static int qmp_pcie_msm8996_power_on(struct phy *phy) */ qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); - if (cfg->has_pwrdn_delay) - usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); + usleep_range(POWER_DOWN_DELAY_US_MIN, POWER_DOWN_DELAY_US_MAX); /* Pull PHY out of reset state */ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);