| Message ID | 20221024105229.v3.5.I418c9eaaf754880fcd2698113e8c3ef821a944d7@changeid (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | mmc: sdhci controllers: Fix SDHCI_RESET_ALL for CQHCI | expand |
On 24/10/22 20:54, Brian Norris wrote: > [[ NOTE: this is completely untested by the author, but included solely > because, as noted in commit df57d73276b8 ("mmc: sdhci-pci: Fix > SDHCI_RESET_ALL for CQHCI for Intel GLK-based controllers"), "other > drivers using CQHCI might benefit from a similar change, if they > also have CQHCI reset by SDHCI_RESET_ALL." We've now seen the same > bug on at least MSM, Arasan, and Intel hardware. ]] > > SDHCI_RESET_ALL resets will reset the hardware CQE state, but we aren't > tracking that properly in software. When out of sync, we may trigger > various timeouts. > > It's not typical to perform resets while CQE is enabled, but this may > occur in some suspend or error recovery scenarios. > > Include this fix by way of the new sdhci_and_cqhci_reset() helper. > > Fixes: 3c4019f97978 ("mmc: tegra: HW Command Queue Support for Tegra SDMMC") > Signed-off-by: Brian Norris <briannorris@chromium.org> This patch is dependent on "mmc: cqhci: Provide helper for resetting both SDHCI and CQHCI". Best point that out in this commit message as well. Otherwise: Acked-by: Adrian Hunter <adrian.hunter@intel.com> > --- > > Changes in v3: > - Use new SDHCI+CQHCI helper > > Changes in v2: > - Drop unnecessary 'enable_hwcq' check > > drivers/mmc/host/sdhci-tegra.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c > index 413925bce0ca..c71000a07656 100644 > --- a/drivers/mmc/host/sdhci-tegra.c > +++ b/drivers/mmc/host/sdhci-tegra.c > @@ -28,6 +28,7 @@ > > #include <soc/tegra/common.h> > > +#include "sdhci-cqhci.h" > #include "sdhci-pltfm.h" > #include "cqhci.h" > > @@ -367,7 +368,7 @@ static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) > const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; > u32 misc_ctrl, clk_ctrl, pad_ctrl; > > - sdhci_reset(host, mask); > + sdhci_and_cqhci_reset(host, mask); > > if (!(mask & SDHCI_RESET_ALL)) > return;
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 413925bce0ca..c71000a07656 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -28,6 +28,7 @@ #include <soc/tegra/common.h> +#include "sdhci-cqhci.h" #include "sdhci-pltfm.h" #include "cqhci.h" @@ -367,7 +368,7 @@ static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; u32 misc_ctrl, clk_ctrl, pad_ctrl; - sdhci_reset(host, mask); + sdhci_and_cqhci_reset(host, mask); if (!(mask & SDHCI_RESET_ALL)) return;
[[ NOTE: this is completely untested by the author, but included solely because, as noted in commit df57d73276b8 ("mmc: sdhci-pci: Fix SDHCI_RESET_ALL for CQHCI for Intel GLK-based controllers"), "other drivers using CQHCI might benefit from a similar change, if they also have CQHCI reset by SDHCI_RESET_ALL." We've now seen the same bug on at least MSM, Arasan, and Intel hardware. ]] SDHCI_RESET_ALL resets will reset the hardware CQE state, but we aren't tracking that properly in software. When out of sync, we may trigger various timeouts. It's not typical to perform resets while CQE is enabled, but this may occur in some suspend or error recovery scenarios. Include this fix by way of the new sdhci_and_cqhci_reset() helper. Fixes: 3c4019f97978 ("mmc: tegra: HW Command Queue Support for Tegra SDMMC") Signed-off-by: Brian Norris <briannorris@chromium.org> --- Changes in v3: - Use new SDHCI+CQHCI helper Changes in v2: - Drop unnecessary 'enable_hwcq' check drivers/mmc/host/sdhci-tegra.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)