| Message ID | 20221102175449.452283-3-dmitry.baryshkov@linaro.org (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | drm/msm: rework msm_iommu_new() and .create_address_space cb | expand |
On Wed, Nov 2, 2022 at 10:54 AM Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote: > > The function a6xx_create_address_space() is mostly a copy of > adreno_iommu_create_address_space() with added quirk setting. Rework > these two functions to be a thin wrappers around a common helper. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Rob Clark <robdclark@gmail.com> > --- > drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 2 +- > drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 2 +- > drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 +- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 28 +------------------------ > drivers/gpu/drm/msm/adreno/adreno_gpu.c | 12 +++++++++-- > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 7 ++++++- > 6 files changed, 20 insertions(+), 33 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c > index 2c8b9899625b..948785ed07bb 100644 > --- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c > @@ -500,7 +500,7 @@ static const struct adreno_gpu_funcs funcs = { > #endif > .gpu_state_get = a3xx_gpu_state_get, > .gpu_state_put = adreno_gpu_state_put, > - .create_address_space = adreno_iommu_create_address_space, > + .create_address_space = adreno_create_address_space, > .get_rptr = a3xx_get_rptr, > }, > }; > diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c > index 7cb8d9849c07..2fb32d5552c4 100644 > --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c > @@ -635,7 +635,7 @@ static const struct adreno_gpu_funcs funcs = { > #endif > .gpu_state_get = a4xx_gpu_state_get, > .gpu_state_put = adreno_gpu_state_put, > - .create_address_space = adreno_iommu_create_address_space, > + .create_address_space = adreno_create_address_space, > .get_rptr = a4xx_get_rptr, > }, > .get_timestamp = a4xx_get_timestamp, > diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > index 3dcec7acb384..3c537c0016fa 100644 > --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > @@ -1705,7 +1705,7 @@ static const struct adreno_gpu_funcs funcs = { > .gpu_busy = a5xx_gpu_busy, > .gpu_state_get = a5xx_gpu_state_get, > .gpu_state_put = a5xx_gpu_state_put, > - .create_address_space = adreno_iommu_create_address_space, > + .create_address_space = adreno_create_address_space, > .get_rptr = a5xx_get_rptr, > }, > .get_timestamp = a5xx_get_timestamp, > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index db4b3a48c708..e87196457b9a 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -1786,10 +1786,6 @@ a6xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev) > { > struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); > struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); > - struct iommu_domain_geometry *geometry; > - struct msm_mmu *mmu; > - struct msm_gem_address_space *aspace; > - u64 start, size; > unsigned long quirks = 0; > > /* > @@ -1799,29 +1795,7 @@ a6xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev) > if (!IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice)) > quirks |= IO_PGTABLE_QUIRK_ARM_OUTER_WBWA; > > - mmu = msm_iommu_new(&pdev->dev, quirks); > - if (IS_ERR_OR_NULL(mmu)) > - return ERR_CAST(mmu); > - > - geometry = msm_iommu_get_geometry(mmu); > - if (IS_ERR(geometry)) > - return ERR_CAST(geometry); > - > - /* > - * Use the aperture start or SZ_16M, whichever is greater. This will > - * ensure that we align with the allocated pagetable range while still > - * allowing room in the lower 32 bits for GMEM and whatnot > - */ > - start = max_t(u64, SZ_16M, geometry->aperture_start); > - size = geometry->aperture_end - start + 1; > - > - aspace = msm_gem_address_space_create(mmu, "gpu", > - start & GENMASK_ULL(48, 0), size); > - > - if (IS_ERR(aspace) && !IS_ERR(mmu)) > - mmu->funcs->destroy(mmu); > - > - return aspace; > + return adreno_iommu_create_address_space(gpu, pdev, quirks); > } > > static struct msm_gem_address_space * > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c > index 12d0497f57e1..12a964dc3b8d 100644 > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c > @@ -191,16 +191,24 @@ int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid) > return zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw, pasid); > } > > +struct msm_gem_address_space * > +adreno_create_address_space(struct msm_gpu *gpu, > + struct platform_device *pdev) > +{ > + return adreno_iommu_create_address_space(gpu, pdev, 0); > +} > + > struct msm_gem_address_space * > adreno_iommu_create_address_space(struct msm_gpu *gpu, > - struct platform_device *pdev) > + struct platform_device *pdev, > + unsigned long quirks) > { > struct iommu_domain_geometry *geometry; > struct msm_mmu *mmu; > struct msm_gem_address_space *aspace; > u64 start, size; > > - mmu = msm_iommu_new(&pdev->dev, 0); > + mmu = msm_iommu_new(&pdev->dev, quirks); > if (IS_ERR_OR_NULL(mmu)) > return ERR_CAST(mmu); > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > index 707273339969..5d4b1c95033f 100644 > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > @@ -335,8 +335,13 @@ void adreno_show_object(struct drm_printer *p, void **ptr, int len, > * attached targets > */ > struct msm_gem_address_space * > +adreno_create_address_space(struct msm_gpu *gpu, > + struct platform_device *pdev); > + > +struct msm_gem_address_space * > adreno_iommu_create_address_space(struct msm_gpu *gpu, > - struct platform_device *pdev); > + struct platform_device *pdev, > + unsigned long quirks); > > int adreno_read_speedbin(struct device *dev, u32 *speedbin); > > -- > 2.35.1 >
diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c index 2c8b9899625b..948785ed07bb 100644 --- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c @@ -500,7 +500,7 @@ static const struct adreno_gpu_funcs funcs = { #endif .gpu_state_get = a3xx_gpu_state_get, .gpu_state_put = adreno_gpu_state_put, - .create_address_space = adreno_iommu_create_address_space, + .create_address_space = adreno_create_address_space, .get_rptr = a3xx_get_rptr, }, }; diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c index 7cb8d9849c07..2fb32d5552c4 100644 --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c @@ -635,7 +635,7 @@ static const struct adreno_gpu_funcs funcs = { #endif .gpu_state_get = a4xx_gpu_state_get, .gpu_state_put = adreno_gpu_state_put, - .create_address_space = adreno_iommu_create_address_space, + .create_address_space = adreno_create_address_space, .get_rptr = a4xx_get_rptr, }, .get_timestamp = a4xx_get_timestamp, diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index 3dcec7acb384..3c537c0016fa 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -1705,7 +1705,7 @@ static const struct adreno_gpu_funcs funcs = { .gpu_busy = a5xx_gpu_busy, .gpu_state_get = a5xx_gpu_state_get, .gpu_state_put = a5xx_gpu_state_put, - .create_address_space = adreno_iommu_create_address_space, + .create_address_space = adreno_create_address_space, .get_rptr = a5xx_get_rptr, }, .get_timestamp = a5xx_get_timestamp, diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index db4b3a48c708..e87196457b9a 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1786,10 +1786,6 @@ a6xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); - struct iommu_domain_geometry *geometry; - struct msm_mmu *mmu; - struct msm_gem_address_space *aspace; - u64 start, size; unsigned long quirks = 0; /* @@ -1799,29 +1795,7 @@ a6xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev) if (!IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice)) quirks |= IO_PGTABLE_QUIRK_ARM_OUTER_WBWA; - mmu = msm_iommu_new(&pdev->dev, quirks); - if (IS_ERR_OR_NULL(mmu)) - return ERR_CAST(mmu); - - geometry = msm_iommu_get_geometry(mmu); - if (IS_ERR(geometry)) - return ERR_CAST(geometry); - - /* - * Use the aperture start or SZ_16M, whichever is greater. This will - * ensure that we align with the allocated pagetable range while still - * allowing room in the lower 32 bits for GMEM and whatnot - */ - start = max_t(u64, SZ_16M, geometry->aperture_start); - size = geometry->aperture_end - start + 1; - - aspace = msm_gem_address_space_create(mmu, "gpu", - start & GENMASK_ULL(48, 0), size); - - if (IS_ERR(aspace) && !IS_ERR(mmu)) - mmu->funcs->destroy(mmu); - - return aspace; + return adreno_iommu_create_address_space(gpu, pdev, quirks); } static struct msm_gem_address_space * diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 12d0497f57e1..12a964dc3b8d 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -191,16 +191,24 @@ int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid) return zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw, pasid); } +struct msm_gem_address_space * +adreno_create_address_space(struct msm_gpu *gpu, + struct platform_device *pdev) +{ + return adreno_iommu_create_address_space(gpu, pdev, 0); +} + struct msm_gem_address_space * adreno_iommu_create_address_space(struct msm_gpu *gpu, - struct platform_device *pdev) + struct platform_device *pdev, + unsigned long quirks) { struct iommu_domain_geometry *geometry; struct msm_mmu *mmu; struct msm_gem_address_space *aspace; u64 start, size; - mmu = msm_iommu_new(&pdev->dev, 0); + mmu = msm_iommu_new(&pdev->dev, quirks); if (IS_ERR_OR_NULL(mmu)) return ERR_CAST(mmu); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 707273339969..5d4b1c95033f 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -335,8 +335,13 @@ void adreno_show_object(struct drm_printer *p, void **ptr, int len, * attached targets */ struct msm_gem_address_space * +adreno_create_address_space(struct msm_gpu *gpu, + struct platform_device *pdev); + +struct msm_gem_address_space * adreno_iommu_create_address_space(struct msm_gpu *gpu, - struct platform_device *pdev); + struct platform_device *pdev, + unsigned long quirks); int adreno_read_speedbin(struct device *dev, u32 *speedbin);
The function a6xx_create_address_space() is mostly a copy of adreno_iommu_create_address_space() with added quirk setting. Rework these two functions to be a thin wrappers around a common helper. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 28 +------------------------ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 12 +++++++++-- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 7 ++++++- 6 files changed, 20 insertions(+), 33 deletions(-)