From patchwork Sun Dec 4 12:45:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13063845 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25AFAC4708E for ; Sun, 4 Dec 2022 12:45:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230007AbiLDMpS (ORCPT ); Sun, 4 Dec 2022 07:45:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48574 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230009AbiLDMpR (ORCPT ); Sun, 4 Dec 2022 07:45:17 -0500 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EE02515FE1 for ; Sun, 4 Dec 2022 04:45:14 -0800 (PST) Received: by mail-lf1-x136.google.com with SMTP id 1so951578lfz.4 for ; Sun, 04 Dec 2022 04:45:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=waDEA8uxNrP4025OcL/yX7LapkcyvqGI/OcJz3TbPaw=; b=SPwYbL3pgXzWQOHY+5VWD7vCjOX6Nf84MGr4jY8I/O8D0Nx18rTi96+WCTOguUC6dL 4NTLltk+f7nLdAt4ciB47L9mAIJd1e+OqlkuebO4eb3NM76zPFm2yu9jSms212Ic+2Xd 5YXjja82gAuWTWMQKgPf5hBs9las2/j4fL+2oXkf3Bht/95gpo/99iAVyHQkp7BIVx4a zQiyCb6yaOiI1TCes6WBSJ5RMWneXaBxLLiwvGrnI3N6HNQu6mThRwTUN1iA6GhnOzWH 5UW+QRm5Wj5kMChFahvZvFPLVimoYsHoSQoGGbpBdFK2qwbpAHH0Wc+eJCDXNstcrtHt dl5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=waDEA8uxNrP4025OcL/yX7LapkcyvqGI/OcJz3TbPaw=; b=fq52FVRvYWE/2c9VgNEwLnHThKMKar+R6IvN6F7JHJKoKXuhLsEJpm7zSoo1eteRW4 kEaE1q8qfn9w5qpkGU1zXGc3Yglo9G4xBsdI26lt3T8DZRDv2oGIZ5Mi1MKjty+LuHGx YiiQzxzdytsPcKcrLw0l8CCdRcB/1HnZqqYYBCLViLixungXNrh3JqG/AKe1QWiXyJxH b0Sb/CtD32StUIBuRY/VUdsKsx+vTPA7vGFF8zaKMJlTluAFt+icD17UHgwJKmuJew1L O0ZLxO60CTXsh2xkmFEHMOF16H7NadHUKSdkr+5biqBmQmuauccmdNGl1tnm85rIm7DD XrHA== X-Gm-Message-State: ANoB5pmnqx/zouP9b6lCL4d7b67yl8BMRbA2BkgK0zVZnhYqPuXVCLyp h9D6qzLzRHOzx5wt/6EP3+ls6g== X-Google-Smtp-Source: AA0mqf4Pyy+o/Q69J9jk+U/mO6gNnRLuVqL2iT/HvuN9o2daCtFJqwY5zEd1ycknMpO51PPDSHerjw== X-Received: by 2002:a05:6512:2591:b0:4ae:c2b5:29c4 with SMTP id bf17-20020a056512259100b004aec2b529c4mr22254218lfb.614.1670157913264; Sun, 04 Dec 2022 04:45:13 -0800 (PST) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id k18-20020a05651239d200b0049771081b10sm1763006lfu.31.2022.12.04.04.45.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Dec 2022 04:45:12 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Neil Armstrong , Konrad Dybcio Subject: [PATCH v4 04/11] clk: qcom: gcc-msm8974: move clock parent tables down Date: Sun, 4 Dec 2022 14:45:01 +0200 Message-Id: <20221204124508.1415713-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221204124508.1415713-1-dmitry.baryshkov@linaro.org> References: <20221204124508.1415713-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Rearrage clock parent tables and PLL declarations (pull parents down and gpll4 up), so that we can use pll hw clock fields in the next commit. Reviewed-by: Neil Armstrong Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-msm8974.c | 98 +++++++++++++++++----------------- 1 file changed, 49 insertions(+), 49 deletions(-) diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c index b847ce852ef8..77f3497265a0 100644 --- a/drivers/clk/qcom/gcc-msm8974.c +++ b/drivers/clk/qcom/gcc-msm8974.c @@ -32,28 +32,6 @@ enum { P_GPLL4, }; -static const struct parent_map gcc_xo_gpll0_map[] = { - { P_XO, 0 }, - { P_GPLL0, 1 } -}; - -static const char * const gcc_xo_gpll0[] = { - "xo", - "gpll0_vote", -}; - -static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { - { P_XO, 0 }, - { P_GPLL0, 1 }, - { P_GPLL4, 5 } -}; - -static const char * const gcc_xo_gpll0_gpll4[] = { - "xo", - "gpll0_vote", - "gpll4_vote", -}; - static struct clk_pll gpll0 = { .l_reg = 0x0004, .m_reg = 0x0008, @@ -81,6 +59,55 @@ static struct clk_regmap gpll0_vote = { }, }; +static struct clk_pll gpll4 = { + .l_reg = 0x1dc4, + .m_reg = 0x1dc8, + .n_reg = 0x1dcc, + .config_reg = 0x1dd4, + .mode_reg = 0x1dc0, + .status_reg = 0x1ddc, + .status_bit = 17, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpll4", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +}; + +static struct clk_regmap gpll4_vote = { + .enable_reg = 0x1480, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "gpll4_vote", + .parent_names = (const char *[]){ "gpll4" }, + .num_parents = 1, + .ops = &clk_pll_vote_ops, + }, +}; + +static const struct parent_map gcc_xo_gpll0_map[] = { + { P_XO, 0 }, + { P_GPLL0, 1 } +}; + +static const char * const gcc_xo_gpll0[] = { + "xo", + "gpll0_vote", +}; + +static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { + { P_XO, 0 }, + { P_GPLL0, 1 }, + { P_GPLL4, 5 } +}; + +static const char * const gcc_xo_gpll0_gpll4[] = { + "xo", + "gpll0_vote", + "gpll4_vote", +}; + static struct clk_rcg2 config_noc_clk_src = { .cmd_rcgr = 0x0150, .hid_width = 5, @@ -144,33 +171,6 @@ static struct clk_regmap gpll1_vote = { }, }; -static struct clk_pll gpll4 = { - .l_reg = 0x1dc4, - .m_reg = 0x1dc8, - .n_reg = 0x1dcc, - .config_reg = 0x1dd4, - .mode_reg = 0x1dc0, - .status_reg = 0x1ddc, - .status_bit = 17, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gpll4", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -}; - -static struct clk_regmap gpll4_vote = { - .enable_reg = 0x1480, - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "gpll4_vote", - .parent_names = (const char *[]){ "gpll4" }, - .num_parents = 1, - .ops = &clk_pll_vote_ops, - }, -}; - static const struct freq_tbl ftbl_gcc_usb30_master_clk[] = { F(125000000, P_GPLL0, 1, 5, 24), { }