| Message ID | 20221205230116.2204-2-mailingradian@gmail.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [1/3] dt-bindings: nvmem: qfprom: add sdm670 compatible | expand |
On Mon, Dec 05, 2022 at 06:01:15PM -0500, Richard Acayan wrote: > Some hardware quirks and capabilities can be determined by reading the > fuse-programmable read-only memory. Add the QFPROM node so consumers > know if they need to do anything extra to support the hardware. > > Signed-off-by: Richard Acayan <mailingradian@gmail.com> > --- > arch/arm64/boot/dts/qcom/sdm670.dtsi | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi > index f93705bc549f..933ad2fabf3a 100644 > --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi > @@ -731,6 +731,13 @@ gcc: clock-controller@100000 { > #power-domain-cells = <1>; > }; > > + qfprom: qfprom@780000 { > + compatible = "qcom,sdm670-qfprom", "qcom,qfprom"; > + reg = <0 0x780000 0 0x1000>; I suspect the qfprom block is inherited from SDM845, if so 0x780000 contains raw, uncorrected data, while 0x784000 contains ECC-corrected versions of these. Please validate and use the same. Also, please pad the address to 8 digits, to make it easier to check the sort order. Thanks, Bjorn > + #address-cells = <1>; > + #size-cells = <1>; > + }; > + > sdhc_1: mmc@7c4000 { > compatible = "qcom,sdm670-sdhci", "qcom,sdhci-msm-v5"; > reg = <0 0x007c4000 0 0x1000>, > -- > 2.38.1 >
On Mon, Dec 05, 2022 at 05:21:03PM -0600, Bjorn Andersson wrote: > On Mon, Dec 05, 2022 at 06:01:15PM -0500, Richard Acayan wrote: >> Some hardware quirks and capabilities can be determined by reading the >> fuse-programmable read-only memory. Add the QFPROM node so consumers >> know if they need to do anything extra to support the hardware. >> >> Signed-off-by: Richard Acayan <mailingradian@gmail.com> >> --- >> arch/arm64/boot/dts/qcom/sdm670.dtsi | 7 +++++++ >> 1 file changed, 7 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi >> index f93705bc549f..933ad2fabf3a 100644 >> --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi >> @@ -731,6 +731,13 @@ gcc: clock-controller@100000 { >> #power-domain-cells = <1>; >> }; >> >> + qfprom: qfprom@780000 { >> + compatible = "qcom,sdm670-qfprom", "qcom,qfprom"; >> + reg = <0 0x780000 0 0x1000>; > > I suspect the qfprom block is inherited from SDM845, if so 0x780000 > contains raw, uncorrected data, while 0x784000 contains ECC-corrected > versions of these. Please validate and use the same. I just compared the qusb2p_hstx_trim values at 0x7801eb and 0x7841eb and this seems to be true. Will change in the next version. > > Also, please pad the address to 8 digits, to make it easier to check the > sort order. Ack. > > Thanks, > Bjorn > >> + #address-cells = <1>; >> + #size-cells = <1>; >> + }; >> + >> sdhc_1: mmc@7c4000 { >> compatible = "qcom,sdm670-sdhci", "qcom,sdhci-msm-v5"; >> reg = <0 0x007c4000 0 0x1000>, >> -- >> 2.38.1 >>
diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index f93705bc549f..933ad2fabf3a 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -731,6 +731,13 @@ gcc: clock-controller@100000 { #power-domain-cells = <1>; }; + qfprom: qfprom@780000 { + compatible = "qcom,sdm670-qfprom", "qcom,qfprom"; + reg = <0 0x780000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + }; + sdhc_1: mmc@7c4000 { compatible = "qcom,sdm670-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x007c4000 0 0x1000>,
Some hardware quirks and capabilities can be determined by reading the fuse-programmable read-only memory. Add the QFPROM node so consumers know if they need to do anything extra to support the hardware. Signed-off-by: Richard Acayan <mailingradian@gmail.com> --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)