| Message ID | 20221206231729.164453-2-mailingradian@gmail.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 7bff6f4351bf82c0b9279fc711b730d2d28b8b8c |
| Headers | show |
| Series | [1/3] dt-bindings: nvmem: qfprom: add sdm670 compatible | expand |
On 07/12/2022 00:17, Richard Acayan wrote: > Some hardware quirks and capabilities can be determined by reading the > fuse-programmable read-only memory. Add the QFPROM node so consumers > know if they need to do anything extra to support the hardware. > > Signed-off-by: Richard Acayan <mailingradian@gmail.com> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > Changes since v1: > - offset address by 0x4000 and zero-pad regs > > arch/arm64/boot/dts/qcom/sdm670.dtsi | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi > index f93705bc549f..c78156e03d93 100644 > --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi > @@ -731,6 +731,13 @@ gcc: clock-controller@100000 { > #power-domain-cells = <1>; > }; > > + qfprom: qfprom@784000 { > + compatible = "qcom,sdm670-qfprom", "qcom,qfprom"; > + reg = <0 0x00784000 0 0x1000>; > + #address-cells = <1>; > + #size-cells = <1>; > + }; > + > sdhc_1: mmc@7c4000 { > compatible = "qcom,sdm670-sdhci", "qcom,sdhci-msm-v5"; > reg = <0 0x007c4000 0 0x1000>,
On Tue, Dec 06, 2022 at 06:17:30PM -0500, Richard Acayan wrote: > Some hardware quirks and capabilities can be determined by reading the > fuse-programmable read-only memory. Add the QFPROM node so consumers > know if they need to do anything extra to support the hardware. > > Signed-off-by: Richard Acayan <mailingradian@gmail.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> PS. Please include a "vN" in the []-part of subject when resubmitting patches. In this case passing -v 2 to git format-patch would do the trick for you. I will pick this up after the upcoming merge window. Thanks, Bjorn > --- > Changes since v1: > - offset address by 0x4000 and zero-pad regs > > arch/arm64/boot/dts/qcom/sdm670.dtsi | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi > index f93705bc549f..c78156e03d93 100644 > --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi > @@ -731,6 +731,13 @@ gcc: clock-controller@100000 { > #power-domain-cells = <1>; > }; > > + qfprom: qfprom@784000 { > + compatible = "qcom,sdm670-qfprom", "qcom,qfprom"; > + reg = <0 0x00784000 0 0x1000>; > + #address-cells = <1>; > + #size-cells = <1>; > + }; > + > sdhc_1: mmc@7c4000 { > compatible = "qcom,sdm670-sdhci", "qcom,sdhci-msm-v5"; > reg = <0 0x007c4000 0 0x1000>, > -- > 2.38.1 >
diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index f93705bc549f..c78156e03d93 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -731,6 +731,13 @@ gcc: clock-controller@100000 { #power-domain-cells = <1>; }; + qfprom: qfprom@784000 { + compatible = "qcom,sdm670-qfprom", "qcom,qfprom"; + reg = <0 0x00784000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + }; + sdhc_1: mmc@7c4000 { compatible = "qcom,sdm670-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x007c4000 0 0x1000>,
Some hardware quirks and capabilities can be determined by reading the fuse-programmable read-only memory. Add the QFPROM node so consumers know if they need to do anything extra to support the hardware. Signed-off-by: Richard Acayan <mailingradian@gmail.com> --- Changes since v1: - offset address by 0x4000 and zero-pad regs arch/arm64/boot/dts/qcom/sdm670.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)